24-Lane 3-Port PCI Express廬
Switch
89PES24N3
Product Brief
Device Overview
The 89HPES24N3 is a member of IDT鈥檚 PRECISE鈩?family of PCI
Express廬 bridging and switching solutions offering the next-generation
I/O interconnect standard. The PES24N3 is a 24-lane, 3-port peripheral
chip that performs PCI Express Base switching with a feature set opti-
mized for high performance applications such as servers, storage, and
communications/networking. It provides high-performance I/O connec-
tivity and switching functions between a PCI Express upstream port and
two downstream ports or peer-to-peer switching between downstream
ports.
x
x
x
round robin algorithms
Static lane reversal on all ports
Polarity inversion
Ability to load device configuration from serial EEPROM
Legacy Support
x
PCI compatible INTx emulation
x
Bus locking
Highly Integrated Solution
x
Integrates 24 2.5 Gbps embedded SerDes, 8B/10B encoder/
decoder (no separate transceivers needed)
x
Incorporates on-chip internal memory for packet buffering
and queueing
x
Requires no external components
Reliability, Availability, and Serviceability (RAS)
Features
x
Internal end-to-end parity protection on all TLPs ensures
data integrity even in systems that do not implement end-to-
end CRC (ECRC)
x
ECRC passed through
x
Supports PCI Express Native Hot-Plug
鈥?Compatible with Hot-Plug I/O expanders used on PC mother-
boards
x
Hot-Swap capable I/O
Features
eatures
High Performance PCI Express Switch
x
24 PCI Express lanes (2.5Gbps), 3 switch ports
x
12 GBps (96 Gbps) aggregate switching throughput
x
Low latency cut-through switch architecture
x
Supports 128 to 2048 byte maximum payload size
x
One virtual channel
x
Fully compliant with PCI Express Base specification
Revision 1.0a
Flexible Architecture with
Numerous Configuration Options
x
Automatic per port link width negotiation to x8, x4, x2 or x1
x
Port arbitration schemes utilizing round robin or weighted
Diagram
Block Diagram
3-Port Switch Core
Frame Buffer
Route Table
Port
Arbitration
Scheduler
Transaction Layer
Data Link Layer
Transaction Layer
Data Link Layer
Transaction Layer
Data Link Layer
Multiplexer / Demultiplexer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Multiplexer / Demultiplexer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Multiplexer / Demultiplexer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
...
...
...
SerDes
SerDes
SerDes
SerDes
SerDes
SerDes
SerDes
SerDes
SerDes
24 PCI Express Lanes
x8 Upstream Port and Two x8 Downstream Ports
Figure 1 Internal Block Diagram
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
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2005 Integrated Device Technology, Inc.
December 22, 2005
DSC 6803
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