鈼?/div>
Flexible Architecture with Numerous Configuration Options
鈥?Port arbitration schemes utilizing round robin or weighted
round robin algorithms
鈥?Supports automatic per port link with negotiation (x4, x2, or x1)
鈥?Supports static lane reversal on all ports
鈥?Supports polarity inversion
鈥?Supports locked transactions, allowing use with legacy soft-
ware
鈥?Ability to load device configuration from serial EEPROM
Highly Integrated Solution
鈥?Requires no external components
鈥?Incorporates on-chip internal memory for packet buffering and
queueing
鈥?Integrates 12 2.5 Gbps embedded SerDes, 8B/10B encoder/
decoder (no separate transceivers needed)
鈼?/div>
Reliability, Availability, and Serviceability (RAS) Features
鈥?Internal end-to-end parity protection on all TLPs ensures data
integrity even in systems that do not implement end-to-end
CRC (ECRC)
鈥?Supports ECRC passed through
鈥?Supports PCI Express Native Hot-Plug
鈥?Compatible with Hot-Plug I/O expanders used on PC moth-
erboards
鈥?Supports Hot-Swap
鈼?/div>
Power Management
鈥?Supports PCI Express Power Management Interface Specifi-
cation, Revision 1.1 (PCI-PM)
鈥?Unused SerDes are disabled
鈥?Supports Advanced Configuration and Power Interface Speci-
fication, Revision 2.0 (ACPI) supporting active link state
鈼?/div>
Testability and Debug Features
鈥?Supports IEEE 1149.6 JTAG
鈥?Built in SerDes Pseudo-Random Bit Stream (PRBS) generator
鈥?Ability to read and write any internal register via the SMBus
鈥?Ability to bypass link training and force any link into any mode
鈥?Provides statistics and performance counters
鈼?/div>
Block Diagram
3-Port Switch Core
Frame Buffer
Route Table
Port
Arbitration
Scheduler
Scheduler
Transaction Layer
Data Link Layer
Multiplexer/Demultiplexer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Transaction Layer
Data Link Layer
Multiplexer/Demultiplexer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Transaction Layer
Data Link Layer
Multiplexer/Demultiplexer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
SerDes SerDes SerDes SerDes
SerDes SerDes SerDes
SerDes
SerDes SerDes SerDes SerDes
12 PCI Express Lanes
One x4 Upstream Port and Two x4 Downstream Ports
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
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2006 Integrated Device Technology, Inc.
February 15, 2006
DSC 6801
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