8-Lane 2-Port Non-Transparent
PCI Express廬 Switch
89HPES8NT2
Product Brief
Device Overview
The 89HPES8NT2 is a member of the IDT PRECISE鈩?family of PCI
Express廬 switching solutions offering the next-generation I/O intercon-
nect standard. The PES8NT2 is a 8-lane, 2-port peripheral chip that
provides high-performance switching and non-transparent bridging
(NTB) functions between a PCIe廬 upstream port and an NTB down-
stream port. The PES8NT2 is a part of the IDT PCIe System Intercon-
nect Products and is intended to be used with IDT PCIe System
Interconnect Switches. Together, the chipset targets multi-host and intel-
ligent I/O applications such as communications, storage, and blade
servers where inter-domain communication is required.
High Performance PCI Express Switch
鈥?/div>
Eight PCI Express lanes (2.5Gbps), two switch ports
鈥?/div>
Delivers 32 Gbps (4 GBps) of aggregate switching capacity
鈥?/div>
Low latency cut-through switch architecture
鈥?/div>
Support for Max Payload size up to 2048 bytes
鈥?/div>
Supports one virtual channel and eight traffic classes
鈥?/div>
PCI Express Base specification Revision 1.0a compliant
鈼?/div>
Flexible Architecture with Numerous Configuration Options
鈥?/div>
Supports automatic per port link width negotiation (x8, x4, x2,
or x1)
鈥?/div>
Static lane reversal on all ports
鈥?/div>
Automatic polarity inversion on all lanes
鈥?/div>
Supports locked transactions, allowing use with legacy soft-
ware
鈼?/div>
Features
鈥?/div>
Ability to load device configuration from serial EEPROM
鈥?/div>
Ability to control device via SMBus
鈼?/div>
Non-Transparent Port
鈥?/div>
Crosslink support on NTB port
鈥?/div>
Four mapping windows supported
鈥?/div>
Each may be configured as a 32-bit memory or I/O window
鈥?/div>
May be paired to form a 64-bit memory window
鈥?/div>
Interprocessor communication
鈥?/div>
Thirty-two inbound and outbound doorbells
鈥?/div>
Four inbound and outbound message registers
鈥?/div>
Two shared scratchpad registers
鈥?/div>
Allows up to sixteen masters to communicate through the non-
transparent port
鈥?/div>
No limit on the number of supported outstanding transactions
through the non-transparent bridge
鈥?/div>
Completely symmetric non-transparent bridge operation
allows similar/same configuration software to be run
鈥?/div>
Supports direct connection to a transparent or non-transparent
port of another switch
鈼?/div>
Highly Integrated Solution
鈥?/div>
Requires no external components
鈥?/div>
Incorporates on-chip internal memory for packet buffering and
queueing
鈥?/div>
Integrates eight 2.5 Gbps embedded full duplex SerDes, 8B/
10B encoder/decoder (no separate transceivers needed)
Block Diagram
2-Port Switch Core
Frame Buffer
Route Table
Port
Arbitration
Scheduler
Transaction Layer
Data Link Layer
Transaction Layer
Data Link Layer
Non-
Transparent
Bridge
Multiplexer / Demultiplexer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Multiplexer / Demultiplexer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
...
...
SerDes
SerDes
SerDes
SerDes
SerDes
SerDes
8 PCI Express Lanes
x4 Upstream Port and One x4 Downstream Port
Figure 1 Internal Block Diagram
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
1 of 3
漏
2007 Integrated Device Technology, Inc.
March 14, 2007
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