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89HPES48T12ZABLI Datasheet

  • 89HPES48T12ZABLI

  • 48-Lane 12-Port PCI Express㈢ Switch

  • 47頁

  • IDT

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48-Lane 12-Port
PCI Express廬 Switch
廬
89HPES48T12
Data Sheet
Device Overview
The 89HPES48T12 is a member of the IDT PRECISE鈩?family of
PCI Express廬 switching solutions. The PES48T12 is a 48-lane, 12-port
peripheral chip that performs PCI Express packet switching with a
feature set optimized for high-performance applications such as servers,
storage, and communications/networking. It provides connectivity and
switching functions between a PCI Express upstream port and up to
eleven downstream ports and supports switching between downstream
ports.
鈼?/div>
Features
鈼?/div>
High Performance PCI Express Switch
鈥?Twelve switch ports
鈥?/div>
Six main ports each of which consists of 8 SerDes
鈥?/div>
Each x8 main port can further bifurcate to 2 x4-ports
鈥?Forty-eight 2.5 Gbps embedded SerDes
鈥?/div>
Supports pre-emphasis and receive equalization on per-port
basis
鈥?Delivers 192 Gbps (24 GBps) of aggregate switching capacity
鈥?Low-latency cut-through switch architecture
鈥?Support for Max Payload Size up to 2048 bytes
鈼?/div>
鈼?/div>
鈥?Supports one virtual channel and eight traffic classes
鈥?PCI Express Base Specification Revision 1.1 compliant
Flexible Architecture with Numerous Configuration Options
鈥?Port arbitration schemes utilizing round robin algorithms
鈥?Automatic per port link width negotiation to x8, x4, x2 or x1
鈥?Automatic lane reversal on all ports
鈥?Automatic polarity inversion on all lanes
鈥?Supports locked transactions, allowing use with legacy soft-
ware
鈥?Ability to load device configuration from serial EEPROM
鈥?Ability to control device via SMBus
Highly Integrated Solution
鈥?Requires no external components
鈥?Incorporates on-chip internal memory for packet buffering and
queueing
鈥?Integrates forty-eight 2.5 Gbps embedded full duplex SerDes,
8B/10B encoder/decoder (no separate transceivers needed)
Reliability, Availability, and Serviceability (RAS) Features
鈥?Redundant upstream port failover capability
鈥?Supports optional PCI Express end-to-end CRC checking
Block Diagram
x8/x4/x2/x1
SerDes
DL/Transaction Layer
Upstream
Route Table
Port
Arbitration
Scheduler
12-Port Switch Core
Frame Buffer
DL/Transaction Layer
DL/Transaction Layer
DL/Transaction Layer
DL/Transaction Layer
DL/Transaction Layer
SerDes
SerDes
SerDes
SerDes
SerDes
x8/x4/x2/x1
x8/x4/x2/x1
x8/x4/x2/x1
x8/x4/x2/x1
x8/x4/x2/x1
48 PCI Express Lanes
Up to 6 x8 ports or 12 x4 Ports
Figure 1 Internal Block Diagram
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
1 of 47
漏
2007 Integrated Device Technology, Inc.
July 19, 2007
DSC 6924

89HPES48T12ZABLI 產(chǎn)品屬性

  • 0現(xiàn)貨

  • 停產(chǎn)

  • PRECISE?

  • 托盤

  • 停產(chǎn)

  • 開關(guān)接口

  • PCI Express

  • 3.3V

  • 1156-BBGA，F(xiàn)CBGA

  • 1156-FCBGA（35x35）

  • 表面貼裝型

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