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89HPES32H8ZAAL Datasheet

  • 89HPES32H8ZAAL

  • 32-Lane 8-Port PCI Express System Interconnect Switch

  • 40頁

  • IDT

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32-Lane 8-Port PCI Express廬
System Interconnect Switch
廬
89HPES32H8
Data Sheet
Device Overview
The 89HPES32H8 is a member of the IDT PRECISE鈩?family of PCI
Express廬 switching solutions. The PES32H8 is a 32-lane, 8-port system
interconnect switch optimized for PCI Express packet switching in high-
performance applications, supporting multiple simultaneous peer-to-
peer traffic flows. Target applications include servers, storage, communi-
cations, and embedded systems.
鈼?/div>
Features
鈼?/div>
High Performance PCI Express Switch
鈥?Eight maximum switch ports
鈥?/div>
Four main ports each of which consists of eight SerDes
鈥?/div>
Each x8 main port can further bifurcate to 2 x4-ports
鈥?Thirty-two 2.5 Gbps embedded SerDes
鈥?/div>
Supports pre-emphasis and receive equalization on per-port
basis
鈥?Delivers 128 Gbps (16 GBps) aggregate switching capacity
鈥?Low-latency cut-through switch architecture
鈥?Support for Max Payload Size up to 2048 bytes
鈥?Supports two virtual channels and eight traffic classes
鈥?PCI Express Base Specification Revision 1.1 compliant
鈼?/div>
鈼?/div>
Flexible Architecture with Numerous Configuration Options
鈥?Port arbitration schemes utilizing round robin algorithms
鈥?Virtual channels arbitration based on priority
鈥?Automatic per port link width negotiation to x8, x4, x2 or x1
鈥?Automatic lane reversal on all ports
鈥?Automatic polarity inversion on all ports
鈥?Supports locked transactions, allowing use with legacy soft-
ware
鈥?Ability to load device configuration from serial EEPROM
鈥?Ability to control device via SMBus
Highly Integrated Solution
鈥?Requires no external components
鈥?Incorporates on-chip internal memory for packet buffering and
queueing
鈥?Integrates thirty-two 2.5 Gbps embedded full duplex SerDes,
8B/10B encoder/decoder (no separate transceivers needed)
Reliability, Availability, and Serviceability (RAS) Features
鈥?Redundant upstream port failover capability
鈥?Internal end-to-end parity protection on all TLPs ensures data
integrity even in systems that do not implement end-to-end
CRC (ECRC)
Block Diagram
x8/x4/x2/x1
x8/x4/x2/x1
SerDes
DL/Transaction Layer
SerDes
DL/Transaction Layer
Route Table
Port
Arbitration
8-Port Switch Core
Frame Buffer
Scheduler
DL/Transaction Layer
DL/Transaction Layer
SerDes
SerDes
x8/x4/x2/x1
x8/x4/x2/x1
Figure 1 Internal Block Diagram
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
1 of 40
漏
2007 Integrated Device Technology, Inc.
July 19, 2007

89HPES32H8ZAAL 產(chǎn)品屬性

  • 0現(xiàn)貨

  • 停產(chǎn)

  • PRECISE?

  • 托盤

  • 停產(chǎn)

  • 開關(guān)接口

  • PCI Express

  • 3.3V

  • 900-BBGA，F(xiàn)CBGA

  • 900-FCBGA（31x31）

  • 表面貼裝型

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