Storage
Solutions
Serial ATA
Bridge Chip Solutions
88i8030
The 88i8030 family of Serial ATA (SATA) bridge chips, the 脼rst offering in the Marvell
簍
family of high-speed interface
input/output (I/O) solutions, allows storage OEMs to take advanced data storage systems to the next level of
performance. By converting Parallel ATA to SATA, the Marvell 88i8030 bridge solution allows Hard Disk Drive
(HDD), motherboard and storage subsystem manufacturers to utilize their current Parallel ATA electronics for
faster time-to-market prior to full industry transition to SATA. The 88i8030 devices are designed to interface to
traditional Parallel ATA HDD controllers as well as to host chipsets running up to 150 MBps. Since the bridge allows
parallel connectivity over short trace distances, the 88i8030 product allows for 150 MBps transfer rates with low
noise and high reliability. The devices employ the latest SATA Physical Layer (PHY) technology, starting with the
SATA Working Group-de脼ned Generation I speed of 1.5 Gbps, and scalable to 3.0 Gbps to support the future
Generation II, Phase II, SATA speed. The 88i8030脮s PHY leverages four generations of production-proven
Serializer/Deserializer (SERDES) technology from its industry-leading Alaska
簍
Gigabit PHY products. The Marvell
bridge device implements user-selectable SSC for reduced EMI in storage systems. This makes the interface
attractive not only as an inside-the-box technology, but also potentially increases its usefulness for out-of-the-box
interconnects in many consumer electronics applications. The 88i8030 products offer premphasis and amplitude
settings with programmable coef脼cients to help ensure signal integrity over extended trace and cable lengths.
This advanced signaling capability allows for optimal performance in many varieties of storage applications.
PHY
UART
FIFO
Test/Debug
CNFG
PLL
Serial ATA
PRODUCT OVERVIEW
Parallel ATA
Link, Transport and
Command Layers
Register
Fig 1. 88i8030 Block Diagram
FEATURES
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Supports both host and device operation
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User-selectable maximum speeds of 66/100/133/150 MBps
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Ultra low power consumption
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Supports spec-de脼ned power management
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Advanced design tolerates +/- 1.5% frequency offset
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User-selectable Spread Spectrum Clocking (SSC) support
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Programmable reference clock settings
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Fully-digital Phase Locked Loop (PLL)
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Pre-emphasis and amplitude settings with programmable coef脼cients
BENEFITS
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Enables faster system development
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Provides 脽exibility in system design
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Helps to extend battery life in mobile applications and lessen cooling
requirements in storage enclosures
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Ef脼cient power consumption control
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Allows for the use of less expensive ceramic resonators, lowering
system cost
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Reduces Electro Magnetic Interference (EMI), key for both storage
systems and PC motherboards
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Increase design 脽exibility
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Reduces sensitivity to process variations, increasing
manufacturability
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Ensure signal integrity over extended backplane distances up to
20+ inches of FR4 trace
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