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80960MC Datasheet

  • 80960MC

  • EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POIN...

  • 401.00KB

  • 39頁

  • INTEL   INTEL

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PRELIMINARY
80960MC
EMBEDDED 32-BIT MICROPROCESSOR
WITH INTEGRATED FLOATING-POINT UNIT
AND MEMORY MANAGEMENT UNIT
Commercial
s
High-Performance Embedded Architecture
s
On-Chip Memory Management Unit
鈥?25 MIPS Burst Execution at 25 MHz
鈥?9.4 MIPS* Sustained Execution at
25 MHz
s
On-Chip Floating Point Unit
鈥?Supports IEEE 754 Floating Point
Standard
鈥?Full Transcendental Support
鈥?Four 80-Bit Registers
鈥?13.6 Million Whetstones/s
(Single Precision) at 25 MHz
s
512-Byte On-Chip Instruction Cache
鈥?Direct Mapped
鈥?Parallel Load/Decode for Uncached
Instructions
s
Multiple Register Sets
鈥?Sixteen Global 32-Bit Registers
鈥?Sixteen Local 32-Bit Registers
鈥?Four Local Register Sets Stored
On-Chip (Sixteen 32-Bit Registers per
Set)
鈥?Register Scoreboarding
s
s
s
s
鈥?4 Gbyte Virtual Address Space per
Task
鈥?4 Kbyte Pages with Supervisor/User
Protection
Built-in Interrupt Controller
鈥?32 Priority Levels
鈥?248 Vectors
鈥?Supports M8259A
鈥?3.4
碌s
Latency @ 25 MHz
Easy to Use, High Bandwidth 32-Bit Bus
鈥?66.7 Mbytes/s Burst
鈥?Up to 16 Bytes Transferred per Burst
Multitasking and Multiprocessor Support
鈥?Automatic Task dispatching
鈥?Prioritized Task Queues
Advanced Package Technology
鈥?132-Lead Ceramic Pin Grid Array
FOUR
80-BIT FP
REGISTERS
80-BIT
FPU
SIXTEEN
32-BIT GLOBAL
REGISTERS
64- BY 32-BIT
LOCAL
REGISTER
CACHE
32-BIT
INSTRUCTION
EXECUTION
UNIT
MMU
32-BIT
BUS CONTROL
LOGIC
INSTRUCTION
FETCH UNIT
512-BYTE
INSTRUCTION
CACHE
INSTRUCTION
DECODER
MICRO-
INSTRUCTION
SEQUENCER
MICRO-
INSTRUCTION
ROM
32-BIT
BURST
BUS
Figure 1. The 80960MC Processor鈥檚 Highly Parallel Architecture
漏 INTEL CORPORATION, 1997
September, 1997
Order Number:
273123-001

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