implementing single- and double-precision operations
achieves 500mflops
鈥?Extremely large on-chip primary cache
鈥?On-chip secondary cache controller
x
MIPS-IV 64-bit ISA for improved computation
鈥?Compound floating-point operations for 3D graphics and
floating-point DSP
鈥?Conditional move operations
x
Large on-chip TLB
x
Active power management, including use of WAIT operation
Large, efficient on-chip caches
鈥?32KB Instruction Cache, 32KB Data Cache
鈥?2-set associative in each cach
鈥?Virtually indexed and physically tagged to minimize cache
flushes
鈥?Write-back and write-through selectable on a per page basis
鈥?Critical word first cache miss processing
鈥?Supports back-to-back loads and stores in any combination at
full pipeline rate
x
High-performance memory system
鈥?Large primary caches integrated on-chip
鈥?Secondary cache control interface on-chip
鈥?High-frequency 64-bit bus interface runs up to 125MHz
鈥?Aggregate bandwidth of on-chip caches, system interface of
5.6GB/s
鈥?High-performance write protocols for graphics and data
communications
x
Compatible with a variety of operating systems
鈥?Windows鈩?CE
鈥?Numerous MIPS-compatible real-time operating systems
x
Uses input system clock, with processor pipeline clock
multiplied by a factor of 2-8
x
Industrial and commercial temperature range
Unpacker/Packer
Floating-point Control
The IDT logo is a registered trademark and RC32134, RC32364, RC64145, RC64474, RC64475, RC4650, RC4640, RC4600,RC4700 RC3081, RC3052, RC3051, RC3041, RISController, and RISCore are trade-
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