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79RC32T351-100DH Datasheet

  • 79RC32T351-100DH

  • MICROPROCESSOR|32-BIT|QFP|208PIN|PLASTIC

  • 42頁(yè)

  • ETC

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Integrated Communications
Processor
79RC32351
Features List
RC32300 32-bit Microprocessor
鈥?Enhanced MIPS-II ISA
鈥?Enhanced MIPS-IV cache prefetch instruction
鈥?DSP Instructions
鈥?MMU with 16-entry TLB
鈥?8kB Instruction cache, 2-way set associative
鈥?2kB Data cache, 2-way set associative
鈥?Per line cache locking
鈥?Write-through and write-back cache management
鈥?Debug interface through the EJTAG port
鈥?Big or little endian support
鈼?/div>
Interrupt Controller
鈥?Allows status of each interrupt to be read and masked
鈼?/div>
UARTs
鈥?Two 16550 Compatible UARTs
鈥?Baud rate support up to 115 Kbits
鈼?/div>
Counter/Timers
鈥?Three general purpose 32-bit counter/timers
鈼?/div>
General Purpose I/O Pins (GPIOP)
鈥?32 individually programmable pins:
each pin programmable as input, output, or alternate function,
input can be an interrupt or NMI source,
input can also be active high or active low
鈥?4 additional, auxiliary GPIO pins can be configured as input or
output
鈼?/div>
SDRAM Controller
鈥?2 memory banks, non-interleaved, 512 MB total
鈥?32-bit wide data path
鈥?Supports 4-bit, 8-bit, and 16-bit wide SDRAM chips
鈥?SODIMM support
鈥?Stays on page between transfers
鈥?Automatic refresh generation
鈼?/div>
Peripheral Device Controller
鈥?26-bit address bus
鈥?32-bit data bus with variable width support of 8-,16-, or 32-bits
鈥?8-bit boot ROM support
鈥?6 banks available, up to 64MB per bank
鈥?Supports Flash ROM, PROM, SRAM, dual-port memory, and
peripheral devices
鈥?Supports external wait-state generation, Intel or Motorola style
鈥?Write protect capability
鈥?Direct control of optional external data transceivers
鈼?/div>
System Integrity
鈥?Programmable system watchdog timer resets system on time-
out
鈥?Programmable bus transaction times memory and peripheral
transactions and generates a warm reset on time-out
鈼?/div>
DMA
鈥?14 DMA channels
鈥?Services on-chip and external peripherals
鈥?Supports memory-to-memory, memory-to-I/O, and I/O-to-I/O
transfers
鈥?Supports flexible descriptor based operation and chaining via
linked lists of records (scatter / gather capability)
鈥?Supports unaligned transfers
鈼?/div>
Block Diagram
RC32300
CPU Core
ICE
EJTAG
D. Cache
MMU
I. Cache
Interrupt
Controller
:
:
Watchdog
Timer
10/100
Ethernet
Interface
USB
Interface
16 Channel
DMA
Controller
Arbiter
3 Counter
Timers
Ext. Bus
Master
SDRAM &
Device
Controller
2 UARTS
(16550)
GPIO
Interface
ATM
Interface
Memory &
Peripheral Bus
Ch. 1 Ch. 2
Serial Channels
GPIO Pins
Utopia 1 / 2
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
1 of 42
錚?/div>
2002 Integrated Device Technology, Inc.
May 20, 2002
DSC 6053

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