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79RC32438 Datasheet

  • 79RC32438

  • IDTTM InterpriseTM Integrated Communications Processor

  • 59頁(yè)

  • IDT

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IDT
TM
Interprise
TM
Integrated
Communications Processor
79RC32438
Features
32-bit CPU Core
鈥?MIPS32 instruction set
鈥?Cache Sizes: 16KB instruction and data caches, 4-Way set
associative, cache line locking, non-blocking prefetches
鈥?16 dual-entry JTLB with variable page sizes
鈥?3-entry instruction TLB
鈥?3-entry data TLB
鈥?Max issue rate of one 32x16 multiply per clock
鈥?Max issue rate of one 32x32 multiply every other clock
鈥?CPU control with start, stop and single stepping
鈥?Software breakpoints support
鈥?Hardware breakpoints on virtual addresses
鈥?Enhanced JTAG and ICE Interface that is compatible with v2.5
of the EJTAG Specification
鈼?/div>
DDR Memory Controller
鈥?Supports up to 2GB of DDR SDRAM
鈥?2 chip selects (each chip select supports 4 internal DDR
banks)
鈥?Supports 16-bit or 32-bit data bus width using 8, 16, or 32-bit
devices
鈥?Supports 64Mb, 128Mb, 256Mb, 512Mb, and 1Gb DDR
SDRAM devices
鈥?Data bus multiplexing support allows interfacing to standard
DDR DIMMs and SODIMMs
鈥?Automatic refresh generation
鈼?/div>
Memory and Peripheral Device Controller
鈥?Provides 鈥済lueless鈥?interface to standard SRAM, Flash, ROM,
dual-port memory, and peripheral devices
鈥?Demultiplexed address and data buses: 16-bit data bus, 26-bit
address bus, 6 chip selects, supports alternate bus masters,
control for external data bus buffers
鈥?Supports 8-bit and 16-bit width devices
Automatic byte gathering and scattering
鈥?Flexible protocol configuration parameters: programmable
number of wait states (0 to 63), programmable postread/post-
write delay (0 to 31), supports external wait state generation,
supports Intel and Motorola style peripherals
鈥?Write protect capability per chip select
鈥?Programmable bus transaction timer generates warm reset
when counter expires
鈥?Supports up to 64 MB of memory per chip select
鈼?/div>
Counter/Timers
鈥?Three general purpose 32-bit counter timers
鈼?/div>
PCI Interface
鈥?32-bit PCI revision 2.2 compliant (3.3V only)
鈥?Supports host or satellite operation in both master and target
modes
鈥?Support for synchronous and asynchronous operation
鈥?PCI clock supports frequencies from 16 MHz to 66 MHz
鈥?PCI arbiter in Host mode: supports 6 external masters, fixed
priority or round robin arbitration
鈥?I
2
O 鈥渓ike鈥?PCI Messaging Unit
鈼?/div>
Block Diagram
MII
MII
MIPS-32
CPU Core
ICE
EJTAG
D. Cache
MMU
I. Cache
Interrupt
Controller
:
:
2 Ethernet
10/100
Interfaces
3 Counter
Timers
IPBus
TM
On-Chip
Memory
DMA
Controller
DDR
DDR &
Device
Controllers
I
2
C
Controller
2 UARTS
(16550)
Arbiter
GPIO
Interface
SPI
Controller
PCI
Master/Target
Interface
PCI Arbiter
(Host Mode)
Memory &
Peripheral Bus
I
2
C Bus
Ch. 1 Ch. 2
Serial Channels
GPIO Pins
SPI Bus
PCI Bus
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
1 of 59
漏
2004 Integrated Device Technology, Inc.
May 25, 2004
DSC 6148

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