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BLOCK DIAGRAM
G.703 compliant line interface for 139.264 Mbps
or 155.52 Mbps CMI-coded coax transmission.
LVPECL compatible line interface for 155.52
Mbps NRZ-coded fiber applications.
Integrated adaptive CMI equalizer and CDR in
receive path.
Serial, LVPECL-compatible system interface
with integrated CDR in transmit path for NRZ to
CMI conversion.
4-bit parallel CMOS system interface with
master/slave Tx clock modes.
Configurable via HW control pins or 4-wire 碌P
interface
Operates from a single reference clock input.
Compliant with ANSI T1.105.03-1994; ITU-T
G.751, G.813, G.823, G.825, G.958; and
Telcordia GR-253-CORE for jitter performance.
Provides Loss of Lock (LOL), CMI Line Code
Violation (LCV), and G.775 compliant Loss of
Signal (LOS) detection.
Receive and Transmit Monitor Modes
Operates from a single 3.3V supply
100-pin TQFP (JEDEC LQFP) package
Lock Detect
SIDP/N
SICKP/N
PICK
PI[3:0]D
PTOCK
SOCKP/N
SODP/N
PO[3:0]D
POCK
CMI-LCV
Detect
CMI
Decoder
Rx CDR
Lock Detect
Adaptive
Eq.
G.775
LOS
Detect
Tx CDR
FIFO
CMI
Encoder
CMI2P/N
CMIP/N
TXCKP/N
ECLP/N
RXP/N
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