NETWORK SEARCH ENGINE
32K x 72 Entries
Datasheet
Brief
75P42100
To request the full IDT75P42100 datasheet, please contact your local
IDT Sales Representative or call 1-831-754-4555
Device Description
IDT provides proven, industry-leading network search engines
(NSEs) and a comprehensive suite of software that enable and accelerate
the intelligent processing of network services in communications equip-
ment. As a part of the complete IDT classification subsystem that includes
content inspection engines, the IDT family of NSEs delivers high-
performance, feature-rich, easy-to-use, integrated search accelerators.
The IDT 75P42100 NSE is a high performance pipelined low-power,
synchronous full-ternary 32K x 72 entry device. Each entry location in
the NSE has both a Data entry and an associated Mask entry. The NSE
devices integrate content addressable memory (CAM) technology with
high-performance logic. The device can perform Lookup and Learn NSE
operations plus Read, Write, Burst Write, and Dual Write maintenance
operations.
The IDT 75P42100 NSE device has a bi-directional bus that is a
multiplexed address and data bus that can support 100 million sustained
searches per second. This device provides array segments which can
be configured to enable multiple width lookups from 36 to 576 bits wide.
The IDT 75P42100 requires a 1.8-volt V
DD
supply, a user selectable 1.8
or 2.5-volt V
DDQ
supply, and a 2.5-volt V
BIAS
supply. This NSE device
provides the user with flexibility and control in determining the device
power. Only the array segments that will be used for a specific NSE
operation are powered up while the unused segments are not.
The IDT 75P42100 NSE utilizes the latest high-performance 1.8V
CMOS processing technology and is packaged in a JEDEC Standard,
thermally enhanced, low profile Ball Grid Array. The options include a
304 BGA, satisfying smaller footprint requirements and a 372 BGA
package that is compatible with the IDT 64K x 72 Entry (75P52100) and
128K x 72 Entry (75K62100) NSE devices.
Block Diagram
LAST NSE
LAST SRAM
Configuration Registers
and
Ram Control Circuits
SRAM CONTROL
ASIC FEEDBACK
CLOCK
PHASE
梅2
CCLK
BURST
Counter
RESET
S
I
Z
E
ARRAY
R/W
Instruction
REQSTB
Command
Bus
NSE
REQUEST
BUS
D
E
C
L
O
G
I
C
P
R
I
O
R
I
T
Y
E
N
C
O
D
E
R
Index
Bus
NSE
RESPONSE
BUS
Request
Data
Bus
Address
O
D
E
Bypass
Comparand Registers
MMOUT
Global Mask Registers
DATA
Result Register
MATCHOUT
534 6 d rw 01
System Configurations
The IDT NSEs are designed to fulfill the needs of various types of
networking systems. In solutions requiring data searching such as
routers, a system configuration as shown in Figure 1.0 may be realized.
Maximum flexibility is provided by allowing one board design to be
populated today using either the IDT 75P42100 or 75P52100 NSEs and
later upgraded to use IDT鈥檚 75K62100 NSE. Applications note AN-279
discusses how to accommodate one board design for any of these NSEs.
In this compatible configuration, the NSE interfaces directly to an
ASIC/ FPGA for lookups and routes an Index to an associated SRAM
device, which supplies the next hop address via an SRAM Data Bus to
the ASIC. The NSE provides the required control signals to directly
hookup to ZBT鈩?or Synchronous Pipeline Burst SRAM. Lookup results
can also be fed directly back to the ASIC/ FPGA without the use of external
SRAM. Control of the associated handshake signals is provided by all
NSEs to adapt to either configuration.
1
漏
2003 Integrated Device Technology, Inc.
All rights reserved.
Figure 1.0 ASIC / Compatible NSE / SRAM configuration
Optional
ASIC
or
FPGA
IDT 75P42100
or
75P52100
or
75K62100
Network Search
Engine
ZBT
or
Sync SRAM
Product specifications subject to change without notice.
Network Interface
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JUNE 2003
DSC-5346/02
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