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74VHCT74AM Datasheet

  • 74VHCT74AM

  • DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR

  • 76.13KB

  • 10頁

  • STMICROELECTRONICS   STMICROELECTRONICS

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廬
74VHCT74A
DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR
s
s
s
s
s
s
s
s
s
HIGH SPEED:
f
MAX
=160 MHz (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 2
碌A
(MAX.) at T
A
= 25
o
C
COMPATIBLE WITH TTL OUTPUTS:
V
IH
= 2V (MIN), V
IL
= 0.8V (MAX)
POWER DOWN PROTECTION ON INPUTS &
OUTPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8 mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
鈮?/div>
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 4.5V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 74
IMPROVED LATCH-UP IMMUNITY
SOP
PACKAGE
SOP
TSSOP
T UBE
74VHCT74AM
TSSOP
T& R
74VHCT74AMTR
74VHCT74ATTR
ORDER CODES
DESCRIPTION
The 74VHCT74A is an advanced high-speed
CMOS DUAL D-TYPE FLIP FLOP WITH
PRESET AND CLEAR fabricated with sub-micron
silicon gate and double-layer metal wiring C
2
MOS
technology.
A signal on the D INPUT is transfered to the Q
OUTPUT during the positive going transition of
the clock pulse.
CLEAR and PRESET are independent of the
clock and accomplished by a low setting on the
appropriate input.
Power down protection is provided on all inputs
and outputs and 0 to 7V can be accepted on
inputs with no regard to the supply voltage. This
device can be used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
March 2000
1/10

74VHCT74AM 產品屬性

  • 55

  • 集成電路 (IC)

  • 邏輯 - 觸發(fā)器

  • 74VHCT

  • 設置（預設）和復位

  • D 型

  • 差分

  • 2

  • 1

  • 140MHz

  • 5.8ns

  • 正邊沿

  • 8mA，8mA

  • 4.5 V ~ 5.5 V

  • -40°C ~ 85°C

  • 表面貼裝

  • 14-SOIC（0.154"，3.90mm 寬）

  • 管件

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