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74VHCT20AM Datasheet

  • 74VHCT20AM

  • DUAL 4-INPUT NAND GATE

  • 7頁(yè)

  • STMICROELECTRONICS   STMICROELECTRONICS

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廬
74VHCT20A
DUAL 4-INPUT NAND GATE
PRELIMINARY DATA
s
s
s
s
s
s
s
s
s
HIGH SPEED: t
PD
= 5 ns (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 2
碌A(chǔ)
(MAX.) at T
A
= 25
o
C
COMPATIBLE WITH TTL OUTPUTS:
V
IH
= 2V (MIN), V
IL
= 0.8V (MAX)
POWER DOWN PROTECTION ON INPUTS &
OUTPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8 mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
鈮?/div>
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 4.5V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 20
IMPROVED LATCH-UP IMMUNITY
SOP
PACKAGE
SOP
TSSOP
T UBE
74VHCT20AM
TSSOP
T& R
74VHCT20AMTR
74VHCT20ATTR
ORDER CODES
DESCRIPTION
The 74VHCT20A is an advanced high-speed
CMOS DUAL 4-INPUT NAND GATE fabricated
with sub-micron silicon gate and double-layer
metal wiring C
2
MOS technology.
The internal circuit is composed of 3 stages
including buffer output, which provide high noise
immunity and stable output.
Power down protection is provided on all inputs
and outputs and 0 to 7V can be accepted on
inputs with no regard to the supply voltage. This
device can be used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
February 2000
1/7

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