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74VHCT139AMTR Datasheet

  • 74VHCT139AMTR

  • DUAL 2 TO 4 DECODER/DEMULTIPLEXER

  • 65.49KB

  • 8頁

  • STMICROELECTRONICS   STMICROELECTRONICS

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廬
74VHCT139A
DUAL 2 TO 4 DECODER/DEMULTIPLEXER
PRELIMINARY DATA
s
s
s
s
s
s
s
s
s
HIGH SPEED: t
PD
= 7.2 ns (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 4
碌A(chǔ)
(MAX.) at T
A
= 25
o
C
COMPATIBLE WITH TTL OUTPUTS:
V
IH
= 2V (MIN), V
IL
= 0.8V (MAX)
POWER DOWN PROTECTION ON INPUTS &
OUTPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8 mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
鈮?/div>
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 4.5V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 139
IMPROVED LATCH-UP IMMUNITY
SOP
PACKAGE
SOP
TSSOP
T UBE
74VHCT139AM
TSSOP
T& R
74VHCT139AMTR
74VHCT139ATTR
ORDER CODES
DESCRIPTION
The 74VHCT139A is an advanced high-speed
CMOS DUAL 2 TO 4 LINE DECODER/
DEMULTIPLEXER fabricated with sub-micron
silicon gate and double-layer metal wiring C
2
MOS
technology.
The active low enable input can be used for
gating or as a data input for demultiplexing
applications. While the enable input is held high,
all four outputs are high independently of the
other inputs.
Power down protection is provided on all inputs
and outputs and 0 to 7V can be accepted on
inputs with no regard to the supply voltage. This
device can be used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
March 2000
1/8

74VHCT139AMTR 產(chǎn)品屬性

  • STMicroelectronics

  • 編碼器、解碼器、復(fù)用器和解復(fù)用器

  • Decoder / Demultiplexer

  • 74V

  • 2 / 4

  • 5.5 V

  • 4.5 V

  • + 125 C

  • SMD/SMT

  • SOP-16

  • Reel

  • - 55 C

  • 2

  • 4

  • 2500

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