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74VHCT132AM Datasheet

  • 74VHCT132AM

  • QUAD 2-INPUT SCHMITT NAND GATE

  • 56.31KB

  • 7頁

  • STMICROELECTRONICS   STMICROELECTRONICS

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廬
74VHCT132A
QUAD 2-INPUT SCHMITT NAND GATE
PRELIMINARY DATA
s
s
s
s
s
s
s
s
s
s
HIGH SPEED: t
PD
= 6.5 ns (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 2
碌A(chǔ)
(MAX.) at T
A
= 25
o
C
TYPICAL HYSTERESIS: 0.7V at V
CC
= 4.5V
POWER DOWN PROTECTION ON INPUTS &
OUTPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8 mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
鈮?/div>
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 4.5V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 132
IMPROVED LATCH-UP IMMUNITY
LOW NOISE: V
OLP
= 0.8V (Max.)
SOP
PACKAGE
SOP
TSSOP
T UBE
74VHCT132AM
TSSOP
T& R
74VHCT132AMTR
74VHCT132ATTR
ORDER CODES
DESCRIPTION
The 74VHCT132A is an advanced high-speed
CMOS QUAD 2-INPUT SCHMITT NAND GATE
fabricated with sub-micron silicon gate and
double-layer metal wiring C
2
MOS technology.
Power down protection is provided on all inputs
and outputs and 0 to 7V can be accepted on
inputs with no regard to the supply voltage. This
device can be used to interface 5V to 3V.
Pin configuration and function are the same as
those of the VHCT00A but the VHCT132A has
hysteresis.
This together with its schmitt trigger function
allows it to be used on line receivers with slow
rise/fall input signals.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
February 2000
1/7

74VHCT132AM 產(chǎn)品屬性

  • STMicroelectronics

  • 門（與/非與/或/非或）

  • NAND

  • 74VHC

  • Quad

  • 2 / 1

  • - 8 mA

  • 8 mA

  • 9.8 ns

  • 5.5 V

  • 4.5 V

  • + 125 C

  • SMD/SMT

  • SOP-14

  • Reel

  • - 55 C

  • 2

  • 1

  • 1000

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