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74VHC574T Datasheet

  • 74VHC574T

  • OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT NON INVERTING

  • 10頁

  • STMICROELECTRONICS   STMICROELECTRONICS

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74VHC574
OCTAL D-TYPE FLIP FLOP
WITH 3 STATE OUTPUT NON INVERTING
s
s
s
s
s
s
s
s
s
s
HIGH SPEED:
f
MAX
= 180 MHz (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 4
碌A(chǔ)
(MAX.) at T
A
= 25
o
C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28% V
CC
(MIN.)
POWER DOWN PROTECTION ON INPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8 mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
鈮?/div>
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 574
IMPROVED LATCH-UP IMMUNITY
LOW NOISE V
OLP
= 0.9V (Max.)
M
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74VHC574M
74VHC574T
at the D inputs.
While the OE input is low, the 8 outputs will be in
a normal logic state (high or low logic level) and,
while high level, the outputs will be in a high
impedance state.
The output control does not affect the internal
operation of flip flop; that is, the old data can be
retained or the new data can be entered even
while the outputs are off.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
DESCRIPTION
The 74VHC574 is an advanced high-speed
CMOS OCTAL D-TYPE FLIP FLOP with 3
STATE OUTPUT NON INVERTING fabricated
with sub-micron silicon gate and double-layer
metal wiring C
2
MOS technology.
This 8 bit D-Type flip-flop is controlled by a clock
input (CK) and an output enable input (OE).
On the positive transition of the clock, the Q
outputs will be set to logic states that were setup
PIN CONNECTION AND IEC LOGIC SYMBOLS
June 1999
1/10

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