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74VHC373T Datasheet

  • 74VHC373T

  • OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING

  • 10頁(yè)

  • STMICROELECTRONICS   STMICROELECTRONICS

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74VHC373
OCTAL D-TYPE LATCH
WITH 3 STATE OUTPUT NON INVERTING
s
s
s
s
s
s
s
s
s
s
HIGH SPEED: t
PD
= 5.0 ns (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 4
碌A(chǔ)
(MAX.) at T
A
= 25
o
C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28% V
CC
(MIN.)
POWER DOWN PROTECTION ON INPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8 mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
鈮?/div>
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 373
IMPROVED LATCH-UP IMMUNITY
LOW NOISE: V
OLP
= 0.9V (Max.)
M
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74VHC373M
74VHC373T
While the LE input is held at a high level, the Q
outputs will follow the data inputs precisely. When
the LE is taken low, the Q outputs will be latched
precisely at the logic level of D input data. While
the (OE) input is low, the 8 outputs will be in a
normal logic state (high or low logic level) and
while high level the outputs will be in a high
impedance state.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
DESCRIPTION
The 74VHC373 is an advanced high-speed
CMOS OCTAL D-TYPE LATCH with 3 STATE
OUTPUT NON INVERTING fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology.
This 8 bit D-Type latch is controlled by a latch
enable input (LE) and an output enable input
(OE).
PIN CONNECTION AND IEC LOGIC SYMBOLS
June 1999
1/10

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