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74VHC16374 Datasheet

  • 74VHC16374

  • 16-BIT D-TYPE FLIP FLOP WITH 3-STATE OUTPUTS NON INVERTING

  • 11頁

  • ETC

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74VHC16374
16-BIT D-TYPE FLIP FLOP
WITH 3-STATE OUTPUTS NON INVERTING
s
s
s
s
s
s
s
s
s
s
HIGH SPEED:
f
MAX
= 185 MHz (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 4
碌A(chǔ)
(MAX.) at T
A
=25擄C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28% V
CC
(MIN.)
POWER DOWN PROTECTION ON INPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8 mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
鈮?/div>
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 16374
IMPROVED LATCH-UP IMMUNITY
LOW NOISE: V
OLP
= 0.9V (MAX.)
TSSOP
ORDER CODES
PACKAGE
TSSOP
TUBE
T&R
74VHC16374TTR
PIN CONNECTION
DESCRIPTION
The 74VHC16374 is an advanced high-speed
FLIP FLOP with 3 STATE OUTPUTS NON
INVERTING fabricated with sub-micron silicon
gate and double-layer metal wiring C
2
MOS
technology.
These 16 bit D-TYPE flip-flop is controlled by two
clock inputs (CK) and two output enable inputs
(nOE). The device can be used as two 8-bit
flip-flops or one 16-bit flip-flop.
On the positive transition of the clock, the Q
outputs will be set to the logic state that were
setup at the D inputs.
While the (OE) input is low, the outputs will be in
a normal logic state (high or low logic level); while
OE is high, the outputs will be in a high impedance
state.
The output control does not affect the internal op-
eration of flip-flops; that is, the old data can be re-
tained or the new data can be entered even while
the outputs are off.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with protec-
tion circuits against static discharge, giving them
2KV ESD immunity and transient excess voltage.
February 2003
1/11

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