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74VHC138T Datasheet

  • 74VHC138T

  • 3 TO 8 LINE DECODER INVERTING

  • 68.13KB

  • 8頁(yè)

  • STMICROELECTRONICS   STMICROELECTRONICS

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74VHC138
3 TO 8 LINE DECODER (INVERTING)
s
s
s
s
s
s
s
s
s
HIGH SPEED: t
PD
=5.7 ns (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 4
碌A(chǔ)
(MAX.) at T
A
= 25
o
C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28% V
CC
(MIN.)
POWER DOWN PROTECTION ON INPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8 mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
鈮?/div>
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 138
IMPROVED LATCH-UP IMMUNITY
M1
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74VHC138M
74VHC138T
G2A or G2B is held high, the decoding function is
inhibited and all the 8 outputs go to high.
Three enable inputs are provided to ease
cascade connection and application of address
decoders for memory systems.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
DESCRIPTION
The 74VHC138 is an advanced high-speed
CMOS 3 TO 8 LINE DECODER (INVERTING)
fabricated with sub-micron silicon gate and
double-layer metal wiring C
2
MOS technology.
If the device is enabled, 3 binary select inputs (A,
B and C) determine which one of the outputs will
go low. If enable input G1 is held low or either
PIN CONNECTION AND IEC LOGIC SYMBOLS
June 1999
1/8

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