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74VHC138MTR Datasheet

  • 74VHC138MTR

  • DECODER/DEMUX|3-TO-8-LINE|HC-CMOS|SOP|16PIN|PLASTIC

  • 9頁

  • ETC

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74VHC138
3 TO 8 LINE DECODER (INVERTING)
s
s
s
s
s
s
s
s
s
HIGH SPEED: t
PD
= 5.7ns (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 4
碌A
(MAX.) at T
A
=25擄C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28% V
CC
(MIN.)
POWER DOWN PROTECTION ON INPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8 mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
鈮?/div>
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 138
IMPROVED LATCH-UP IMMUNITY
SOP
TSSOP
ORDER CODES
PACKAGE
SOP
TSSOP
TUBE
74VHC138M
T&R
74VHC138MTR
74VHC138TTR
DESCRIPTION
The 74VHC138 is an advanced high-speed
CMOS 3 TO 8 LINE DECODER (INVERTING)
fabricated with sub-micron silicon gate and
double-layer metal wiring C
2
MOS technology.
If the device is enabled, 3 binary select (A, B, and
C) determine which one of the outputs will go low.
If enable input G1 is held low or either G2A or G2B
is held high, the decoding function is inhibited and
all the 8 outputs go to high.
Tree enable inputs are provided to ease cascade
connection and application of address decoders
for memory systems.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
June 2001
1/9

74VHC138MTR 產(chǎn)品屬性

  • 74VHC138 View All Specifications

  • 2,500

  • 集成電路 (IC)

  • 邏輯 - 信號開關，多路復用器，解碼器

  • 74VHC

  • 解碼器

  • 1 x 3:8

  • 1

  • 8mA，8mA

  • 單電源

  • 2 V ~ 5.5 V

  • -55°C ~ 125°C

  • 表面貼裝

  • 16-SOIC（0.154"，3.90mm 寬）

  • 16-SOP

  • 帶卷 (TR)

  • 497-1103-2

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