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74VHC126T Datasheet

  • 74VHC126T

  • QUAD BUS BUFFERS (3-STATE)

  • 8頁(yè)

  • STMICROELECTRONICS   STMICROELECTRONICS

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74VHC126
QUAD BUS BUFFERS (3-STATE)
PRELIMINARY DATA
s
s
s
s
s
s
s
s
s
s
HIGH SPEED: t
PD
= 3.8 ns (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 4
碌A(chǔ)
(MAX.) at T
A
= 25
o
C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28% V
CC
(MIN.)
POWER DOWN PROTECTION ON INPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8 mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
鈮?/div>
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 126
IMPROVED LATCH-UP IMMUNITY
LOW NOISE: V
OLP
= 0.8V (Max.)
M
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74VHC126M
74VHC126T
This device requires the 3-STATE control input G
to be set low to place the output into the high
impedance state.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
DESCRIPTION
The 74VHC126 is an advanced high-speed
CMOS QUAD BUS BUFFERS fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology.
PIN CONNECTION AND IEC LOGIC SYMBOLS
June 1999
1/8

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