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74VHC03M Datasheet

  • 74VHC03M

  • QUAD 2-INPUT OPEN DRAIN NAND GATE

  • 57.32KB

  • 7頁

  • STMICROELECTRONICS   STMICROELECTRONICS

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74VHC03
QUAD 2-INPUT OPEN DRAIN NAND GATE
PRELIMINARY DATA
s
s
s
s
s
s
s
s
HIGH SPEED: t
PD
= 3.7 ns (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 2
碌A(chǔ)
(MAX.) at T
A
= 25
o
C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28% V
CC
(MIN.)
POWER DOWN PROTECTION ON INPUTS
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 03
IMPROVED LATCH-UP IMMUNITY
LOW NOISE: V
OLP
= 0.8V (Max.)
M
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74VHC03M
74VHC03T
be used in wired AND configuration. This device
can also be used as a led driver and in any other
application requiring a current sink.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2kV ESD immunity and transient excess
voltage.
DESCRIPTION
The 74VHC03 is an advanced high-speed CMOS
QUAD 2-INPUT OPEN DRAIN NAND GATE
fabricated with sub-micron silicon gate and
double-layer metal wiring C
2
MOS technology.
The internal circuit is composed of 3 stages
including buffer output, which provides high noise
immunity and stable output.
This device can, with an external pull-up resistor,
PIN CONNECTION AND IEC LOGIC SYMBOLS
June 1999
1/7

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