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74VCXH162374T Datasheet

  • 74VCXH162374T

  • 16-Bit D-Type Flip-Flop

  • 10頁(yè)

  • ETC

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74VCXH162374
LOW VOLTAGE 16-BIT D-TYPE FLIP FLOP (3-STATE)
WITH 3.6V TOLERANT INPUTS AND OUTPUTS
s
s
s
s
s
s
s
s
s
3.6V TOLERANT INPUTS AND OUTPUTS
HIGH SPEED:
t
PD
= 3.4 ns (MAX.) at V
CC
= 3.0 to 3.6V
t
PD
= 4.8 ns (MAX.) at V
CC
= 2.3 to 2.7V
POWER-DOWN PROTECTION ON INPUTS
AND OUTPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 12 mA (MIN) at V
CC
= 3.0V
|I
OH
| = I
OL
= 8 mA (MIN) at V
CC
= 2.3V
26鈩?SERIE RESISTORS IN OUTPUTS
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 1.8V to 3.6V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 16374
LATCH-UP PERFORMANCE EXCEEDS 300mA
ESD PERFORMANCE:
HBM >2000V; MM > 200V
T
(TSSOP48 Package)
ORDER CODES :
74VCXH162374T
PIN CONNECTION
DESCRIPTION
The VCXH162374 is a low voltage CMOS 16-BIT
D-TYPE FLIP FLOP with 3 STATE OUTPUT NON
INVERTING fabricated with sub-micron silicon gate
and five-layer metal wiring C2MOS technology. It is
ideal for low power and very high speed 2.3 to 3.6V
applications; it can be interfaced to 3.6V signal
enviroment for both inputs and outputs.
These 16 bit D-Type flip-flops are controlled by
two clock inputs (nCK) and two output enable
inputs (nOE). On the positive transition of the
(nCK), the nQ outputs will be set to the logic state
that were setup at the nD inputs. While the (nOE)
input is low, the 8 outputs (nQ) will be in a normal
state (high or low logic level) and while high level
the outputs will be in a high impedance state. Any
output control does not affect the internal operation
of flip flops; that is, the old data can be retained or
the new data can be entered even while the
outputs are off. This device is designed to be used
with 3 state memory address drivers, etc.
The device circuits is including 26鈩?series
resistance in the outputs. These resistors permit
to reduce line noise in high speed applications.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
December 1999
1/10

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