74VCXH162373 Low Voltage 16-Bit Transparent Latch with Bushold
January 2000
Revised March 2000
74VCXH162373
Low Voltage 16-Bit Transparent Latch with Bushold
and 26鈩?Series Resistors in Outputs
General Description
The VCXH162373 contains sixteen non-inverting latches
with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. The flip-flops
appear to be transparent to the data when the Latch enable
(LE) is HIGH. When LE is LOW, the data that meets the
setup time is latched. Data appears on the bus when the
Output Enable (OE) is LOW. When OE is HIGH, the out-
puts are in a high impedance state.
The VCXH162373 data inputs include active bushold cir-
cuitry, eliminating the need for external pull-up resistors to
hold unused or floating data inputs at a valid logic level.
The VCXH162373 is also designed with 26鈩?series resis-
tors in the outputs. This design reduces line noise in appli-
cations such as memory address driver, clock drivers and
bus transceivers/transmitters.
The 74VCXH162373 is designed for low voltage (1.65V to
3.6V) V
CC
applications with output compatibility up to 3.6V.
The 74VCXH162373 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s
1.65V鈥?.6V V
CC
supply operation
s
3.6V tolerant control inputs and outputs
s
Bushold on data inputs eliminates the need for external
pull-up/pull-down resistors
s
26鈩?series resistors in outputs
s
t
PD
(I
n
to O
n
)
3.3 ns max for 3.0V to 3.6V V
CC
4.5 ns max for 2.3V to 2.7V V
CC
9.0 ns max for 1.65V to 1.95V V
CC
s
Static Drive (I
OH
/I
OL
)
鹵12
mA @ 3.0V V
CC
鹵8
mA @ 2.3V V
CC
鹵3
mA @ 1.65V V
CC
s
Uses patented noise/EMI reduction circuitry
s
Latch-up performance exceeds 300 mA
s
ESD performance:
Human body model
>
2000V
Machine model
>
200V
Ordering Code:
Ordering Number
74VCXH162373MTD
74VCXH162373MTX
(Note 1)
Package
Number
MTD48
MTD48
Package Description
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TUBES]
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TAPE and REEL]
Note 1:
Use this Order Number to receive devices in Tape and Reel.
Logic Symbol
Pin Descriptions
Pin Names
OE
n
LE
n
I
0
鈥揑
15
O
0
鈥揙
15
Description
Output Enable Input (Active LOW)
Latch Enable Input
Bushold Inputs
Outputs
漏 2000 Fairchild Semiconductor Corporation
DS500227
www.fairchildsemi.com
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