2.5V). The B Port interfaces with the
鈭?/div>
3.3V). Also the VCX164245 is
designed so that the control pins (T/R
n
, OE
n
) are supplied
by V
CCB
.
The 74VCX164245 is suitable for mixed voltage applica-
tions such as notebook computers using a 1.8V CPU and
3.3V peripheral components. It is fabricated with an
Advanced CMOS technology to achieve high speed opera-
tion while maintaining low CMOS power dissipation.
Features
s
Bidirectional interface between busses ranging from
1.65V to 3.6V
s
Supports Live Insertion and Withdrawal (Note 1)
s
Static Drive (I
OH
/I
OL
)
鹵
24 mA @ 3.0V V
CC
鹵
18 mA @ 2.3V V
CC
鹵
6 mA @ 1.65V V
CC
s
Uses patented noise/EMI reduction circuitry
s
Functionally compatible with 74 series 16245
s
Latchup performance exceeds 300 mA
s
ESD performance:
Human Body Model
>
2000V
Machine model
>
200V
s
Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA)
Note 1:
To ensure the high impedance state during power up or power
down, OE
n
should be tied to V
CCB
through a pull up resistor. The minimum
value of the resistor is determined by the current sourcing capability of the
driver.
Ordering Code:
Order Number
74VCX164245GX
(Note 2)
74VCX164245MTD
(Note 3)
Package Number
BGA54A
MTD48
Package Description
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[Tape and Reel]
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 2:
BGA package available in Tape and Reel only.
Note 3:
Device also available in Tape and Reel. Specify by appending suffix letter 鈥淴鈥?to the ordering code.
Logic Diagram
漏 2001 Fairchild Semiconductor Corporation
DSR500159
www.fairchildsemi.com