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74VCX1632245 Datasheet

  • 74VCX1632245

  • 16-BIT DUAL SUPPLY BUS TRANSCEIVER LEVEL TRANSLATOR WITH A S...

  • 15頁

  • STMICROELECTRONICS   STMICROELECTRONICS

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74VCX1632245
16-BIT DUAL SUPPLY BUS TRANSCEIVER
LEVEL TRANSLATOR WITH A SIDE SERIES RESISTOR
s
s
s
s
s
s
s
s
s
s
HIGH SPEED: t
PD
= 4.4ns (MAX.) at T
A
=85擄C
V
CCA
= 3.0V V
CCB
= 2.3V
LOW POWER DISSIPATION:
I
CCA
= I
CCB
= 20碌A(chǔ)(MAX.) at T
A
=85擄C
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OHA
| = I
OLA
= 8mA MIN at
V
CCA
= 3.0V V
CCB
= 1.65V or 2.3V
|I
OHA
| = I
OLA
= 18mA MIN at
V
CCA
= 2.3V V
CCB
= 1.65V)
BALANCED PROPAGATION DELAYS:
t
PLH
鈮?/div>
t
PHL
POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
26鈩?SERIES RESISTOR ON A SIDE OUTPUTS
OPERATING VOLTAGE RANGE:
V
CCA
(OPR) = 2.3V to 3.6V (1.2V Data
Retention)
V
CCB
(OPR) = 1.65V to 2.7V (1.2V Data
Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 16245
LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17)
ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
TSSOP
TFBGA
碌TFBGA
ORDER CODES
PACKAGE
TRAY
T&R
74VCX1632245TTR
74VCX1632245LBR
74VCX1632245TBR
TSSOP48
TFBGA54 74VCX1632245LB
碌TFBGA42
74VCX1632245TB
LOGIC DIAGRAM
DESCRIPTION
The 74VCX1632245 is a dual supply low voltage
CMOS 16-BIT BUS TRANSCEIVER fabricated
with sub-micron silicon gate and five-layer metal
wiring C
2
MOS technology. Designed for use as an
interface between a 3.3V bus and a 2.5V or 1.8V
bus in a mixed 3.3V/1.8V,3.3V/2.5V and 2.5V/
1.8V supply systems, it achieves high speed
operation while maintaining the CMOS low power
dissipation.
This IC is intended for two-way asynchronous
communication between data buses and the
direction of data transmission is determined by
nDIR inputs. The enable inputs nG can be used to
disable the device so that the buses are effectively
isolated. The A-port interfaces with the 3V bus, the
B-port with the 2.5V and 1.8V bus.
All inputs are equipped with protection circuits
against static discharge, giving them 2KV ESD im-
munity and transient excess voltage. All floating
bus terminals during High Z State must be held
HIGH or LOW.
September 2003
n = 1, 2
1/15

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