74VCX16244
Low-Voltage 1.8/2.5/3.3V
16-Bit Buffer
With 3.6 V鈥揟olerant Inputs and Outputs
(3鈥揝tate, Non鈥揑nverting)
The 74VCX16244 is an advanced performance, non鈥搃nverting
16鈥揵it buffer. It is designed for very high鈥搒peed, very low鈥損ower
operation in 1.8 V, 2.5 V or 3.3 V systems.
When operating at 2.5 V (or 1.8 V) the part is designed to tolerate
voltages it may encounter on either inputs or outputs when interfacing
to 3.3 V busses. It is guaranteed to be over鈥搗oltage tolerant to 3.6 V.
The 74VCX16244 is nibble controlled with each nibble functioning
identically, but independently. The control pins may be tied together to
obtain full 16鈥揵it operation. The 3鈥搒tate outputs are controlled by an
Output Enable (OEn) input for each nibble. When OEn is LOW, the
outputs are on. When OEn is HIGH, the outputs are in the high
impedance state.
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MARKING DIAGRAM
48
48
1
74VCX16244DT
AWLYYWW
TSSOP鈥?8
DT SUFFIX
CASE 1201
A
WL
YY
WW
1
鈥?/div>
Designed for Low Voltage Operation: V
CC
= 1.65鈥?.6 V
鈥?/div>
3.6 V Tolerant Inputs and Outputs
鈥?/div>
High Speed Operation: 2.5 ns max for 3.0 to 3.6 V
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
3.0 ns max for 2.3 to 2.7 V
6.0 ns max for 1.65 to 1.95 V
Static Drive:
鹵24
mA Drive at 3.0 V
鹵18
mA Drive at 2.3 V
鹵6
mA Drive at 1.65 V
Supports Live Insertion and Withdrawal
I
OFF
Specification Guarantees High Impedance When V
CC
= 0 V
Near Zero Static Supply Current in All Three Logic States (20
碌A(chǔ))
Substantially Reduces System Power Requirements
Latchup Performance Exceeds
鹵250
mA @ 125擄C
ESD Performance: Human Body Model >2000 V; Machine Model >200 V
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Device
74VCX16244DT
74VCX16244DTR
Package
TSSOP
TSSOP
Shipping
39 / Rail
2500 / Reel
漏
Semiconductor Components Industries, LLC, 2001
1
January, 2001 鈥?Rev. 1
Publication Order Number:
74VCX16244/D
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