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74V2G07CTR Datasheet

  • 74V2G07CTR

  • TRIPLE BUFFER (OPEN DRAIN)

  • 193.55KB

  • 9頁

  • STMICROELECTRONICS   STMICROELECTRONICS

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74V2G07
TRIPLE BUFFER (OPEN DRAIN)
PRELIMINARY DATA
s
s
s
s
s
s
HIGH SPEED: t
PD
=3.7ns (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 1碌A(chǔ)(MAX.) at T
A
=25擄C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28% V
CC
(MIN.)
POWER DOWN PROTECTION ON INPUT
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 5.5V
IMPROVED LATCH-UP IMMUNITY
SOT23-8L
SOT323-8L
ORDER CODES
PACKAGE
SOT23-8L
SOT323-8L
T&R
74V2G07STR
74V2G07CTR
DESCRIPTION
The 74V2G07 is an advanced high-speed CMOS
TRIPLE BUFFER (OPEN DRAIN) fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology.
The internal circuit is composed of 2 stages
including buffer output, which provide high noise
immunity and stable output.
Power down protection is provided on input and 0
to 7V can be accepted on input with no regard to
the supply voltage. This device can be used to
interface 5V to 3V.
PIN CONNECTION AND IEC LOGIC SYMBOLS
November 2001
1/9
This is preliminary information on a new product now in development are or undergoing evaluation. Details subject to change without notice.

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