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74V1T77CTR Datasheet

  • 74V1T77CTR

  • SINGLE D-TYPE LATCH

  • 211.34KB

  • 10頁(yè)

  • STMICROELECTRONICS   STMICROELECTRONICS

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74V1T77
SINGLE D-TYPE LATCH
s
s
s
s
s
s
s
s
HIGH SPEED: t
PD
= 4.7ns (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 1碌A(chǔ)(MAX.) at T
A
=25擄C
COMPATIBLE WITH TTL OUTPUTS:
V
IH
= 2V (MIN), V
IL
= 0.8V (MAX)
POWER DOWN PROTECTION ON INPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8mA (MIN) at V
CC
= 4.5V
BALANCED PROPAGATION DELAYS:
t
PLH
鈮?/div>
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 4.5V to 5.5V
IMPROVED LATCH-UP IMMUNITY
SOT23-5L
SOT323-5L
ORDER CODES
PACKAGE
SOT23-5L
SOT323-5L
T&R
74V1T77STR
74V1T77CTR
DESCRIPTION
The 74V1T77 is an advanced high-speed CMOS
SINGLE D-TYPE LATCH fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology. It is designed to
operate from 4.5V to 5.5V, making this device
ideal for portable applications.
The single D-Type latch is controlled by an Latch
Enable Input (LE). While the LE input is held at a
high level, the Q output will follow the data input
precisely. When the LE input is taken low the Q
output is latched precisely at the logic level of D
data input.
Power down protection is provided on inputs and
0 to 7V can be accepted on inputs with no regard
to the supply voltage. This device can be used to
interface 5V to 3V.
It鈥檚 available in the commercial and extended
temperature range.
All inputs and output are equipped with protection
circuits against static discharge, giving them ESD
immunity and transient excess voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
July 2001
1/10

74V1T77CTR 產(chǎn)品屬性

  • STMicroelectronics

  • 閉鎖

  • 1

  • D-Type Latch

  • 74V

  • Non-Inverting

  • 1

  • - 8 mA

  • 32 mA

  • 7 ns at 5 V

  • 5.5 V

  • 4.5 V

  • + 125 C

  • - 55 C

  • SOT-323-5

  • Reel

  • SMD/SMT

  • 1

  • 3000

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