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74V1T03C Datasheet

  • 74V1T03C

  • SINGLE 2-INPUT OPEN DRAIN NAND GATE

  • 7頁

  • STMICROELECTRONICS   STMICROELECTRONICS

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廬
74V1T03
SINGLE 2-INPUT OPEN DRAIN NAND GATE
PRELIMINARY DATA
s
s
s
s
s
s
HIGH SPEED: t
PD
= 7 ns (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 1
碌A(chǔ)
(MAX.) at T
A
= 25
o
C
COMPATIBLE WITH TTL OUTPUTS:
V
IH
= 2V (MIN), V
IL
= 0.8V (MAX)
POWER DOWN PROTECTION ON INPUTS
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 4.5V to 5.5V
IMPROVED LATCH-UP IMMUNITY
S
(SOT23-5L)
C
(SC-70)
ORDER CODE:
74V1T03S
74V1T03C
This device can, with an external pull-up resistor,
be used in wired AND configuration. This device
can also be used as a led driver in any other
application requiring a current sink.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
DESCRIPTION
The 74V1T03 is an advanced high-speed CMOS
SINGLE 2-INPUT OPEN DRAIN NAND GATE
fabricated with sub-micron silicon gate and
double-layer metal wiring C
2
MOS technology.
The internal circuit is composed of 3 stages
including buffer output, which provide high noise
immunity and stable output.
PIN CONNECTION AND IEC LOGIC SYMBOLS
September 1999
1/7

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