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74V1T02S Datasheet

  • 74V1T02S

  • SINGLE 2-INPUT NOR GATE

  • 51.25KB

  • 7頁

  • STMICROELECTRONICS   STMICROELECTRONICS

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廬
74V1T02
SINGLE 2-INPUT NOR GATE
s
s
s
s
s
s
s
s
HIGH SPEED: t
PD
= 3.5 ns (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 1
碌A
(MAX.) at T
A
= 25
o
C
COMPATIBLE WITH TTL OUTPUTS:
V
IH
= 2V (MIN), V
IL
= 0.8V (MAX)
POWER DOWN PROTECTION ON INPUTS &
OUTPUT
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8 mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
鈮?/div>
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 4.5V to 5.5V
IMPROVED LATCH-UP IMMUNITY
S
(SOT23-5L)
C
(SC-70)
ORDER CODE:
74V1T02S
74V1T02C
wiring C
2
MOS technology.
The internal circuit is composed of 3 stages
including buffer output, which provide high noise
immunity and stable output.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
DESCRIPTION
The 74V1T02 is an advanced high-speed CMOS
SINGLE 2-INPUT NOR GATE fabricated with
sub-micron silicon gate and double-layer metal
PIN CONNECTION AND IEC LOGIC SYMBOLS
October 1999
1/7

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