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74SSTVF32852ZKFR Datasheet

  • 74SSTVF32852ZKFR

  • 24-BIT TO 48-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OU...

  • 11頁

  • TI

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SN74SSTVF32852
24-BIT TO 48-BIT REGISTERED BUFFER
WITH SSTL_2 INPUTS AND OUTPUTS
SCES426A 鈥?FEBRUARY 2003 鈥?REVISED MARCH 2003
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Member of the Texas Instruments
Widebus錚?Family
Operates at 2.3 V to 2.7 V for PC1600,
PC2100, and PC2700; 2.5 V to 2.7 V for
PC3200
Pinout and Functionality Compatible With
JEDEC Standard SSTV32852
Pinout Optimizes 1U DDR DIMM Layout
600 ps Faster (Simultaneous Switching)
Than the JEDEC Standard SSTV32852 in
PC2700 DIMM Applications
1-to-2 Outputs Support Stacked DDR
DIMMs
One Device Per DIMM Required
Output Edge-Control Circuitry Minimizes
Switching Noise in an Unterminated Line
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Outputs Meet SSTL_2 Class I
Specifications
Supports SSTL_2 Data Inputs
Differential Clock (CLK and CLK) Inputs
Supports LVCMOS Switching Levels on the
RESET Input
RESET Input Disables Differential Input
Receivers, Resets All Registers, and
Forces All Outputs Low
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
鈥?2000-V Human-Body Model (A114-A)
鈥?200-V Machine Model (A115-A)
鈥?1000-V Charged-Device Model (C101)
description/ordering information
This 24-bit to 48-bit registered buffer is designed for 2.3-V to 2.7-V V
CC
operation.
All inputs are SSTL_2, except the LVCMOS reset (RESET) input. All outputs are edge-controlled circuits,
optimized for unterminated DIMM loads, and meet SSTL_2 Class I specifications.
The SN74SSTVF32852 operates from a differential clock (CLK and CLK). Data are registered at the crossing
of CLK going high and CLK going low.
The device supports low-power standby operation. When RESET is low, the differential input receivers are
disabled, and undriven (floating) data, clock, and reference voltage (V
REF
) inputs are allowed. In addition, when
RESET is low, all registers are reset and all outputs are forced low. The LVCMOS RESET input always must
be held at a valid logic high or low level.
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in
the low state during power up.
ORDERING INFORMATION
TA
0擄C to 70擄C
PACKAGE鈥?/div>
LFBGA 鈥?GKF
Tape and reel
ORDERABLE
PART NUMBER
SN74SSTVF32852KR
TOP-SIDE
MARKING
SVF852
鈥?Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
錚?/div>
2003, Texas Instruments Incorporated
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
1

74SSTVF32852ZKFR 產(chǎn)品屬性

  • 1,000

  • 集成電路 (IC)

  • 邏輯 - 緩沖器，驅(qū)動(dòng)器，接收器，收發(fā)器

  • 74SSTVF

  • 24 位至 48 位寄存緩沖器

  • 1

  • 24

  • 8mA，8mA

  • 2.3 V ~ 2.7 V

  • 0°C ~ 70°C

  • 表面貼裝

  • 114-BGA Microstar

  • 114-BGA MICROSTAR（16x5.5）

  • 帶卷 (TR)

  • 296-18355-2

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