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74LVX86T Datasheet

  • 74LVX86T

  • Quad 2-input Exclusive OR (XOR) Gate

  • 8頁(yè)

  • ETC

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廬
74LVX86
LOW VOLTAGE CMOS QUAD EXCLUSIVE OR GATE
s
s
s
s
s
s
s
s
s
HIGH SPEED: t
PD
= 5.8 ns (TYP.) at V
CC
= 3.3V
INPUT VOLTAGE LEVEL:
V
IL
= 0.8V, V
IH
= 2V at V
CC
= 3V
LOW POWER DISSIPATION:
I
CC
= 2
碌A(chǔ)
(MAX.) at T
A
= 25
o
C
LOW NOISE:
V
OLP
= 0.3 V (TYP.) at V
CC
= 3.3V
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 4 mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
鈮?/div>
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V (1.2V Data Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 86
IMPROVED LATCH-UP IMMUNITY
M
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74LVX86M
74LVX86T
It has better speed performance at 3.3V than 5V
LS-TTL family combined with the true CMOS low
power consumption.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
DESCRIPTION
The 74LVX86 is a low voltage CMOS QUAD
EXCLUSIVE OR GATE fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology. It is ideal for low
power and low noise 3.3V applications.
PIN CONNECTION AND IEC LOGIC SYMBOLS
March 1999
1/8

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