音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

74LVX374T Datasheet

  • 74LVX374T

  • Octal D-Type Flip-Flop

  • 10頁(yè)

  • ETC

掃碼查看芯片數(shù)據(jù)手冊(cè)

上傳產(chǎn)品規(guī)格書(shū)

PDF預(yù)覽

廬
74LVX374
LOW VOLTAGE OCTAL D-TYPE FLIP FLOP
(3-STATE NON INV.) WITH 5V TOLERANT INPUTS
s
s
s
s
s
s
s
s
s
s
s
HIGH SPEED:
f
MAX
= 160 MHz (TYP.) at V
CC
= 3.3V
5V TOLERANT INPUTS
POWER-DOWN PROTECTION ON INPUTS
INPUT VOLTAGE LEVEL:
V
IL
= 0.8V, V
IH
= 2V at V
CC
= 3V
LOW POWER DISSIPATION:
I
CC
= 4
碌A(chǔ)
(MAX.) at T
A
= 25
o
C
LOW NOISE:
V
OLP
= 0.3 V (TYP.) at V
CC
= 3.3V
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 4 mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
鈮?/div>
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 374
IMPROVED LATCH-UP IMMUNITY
M
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74LVX374M
74LVX374T
outputs will be set to the logic state that were
setup at the D inputs.
While the (OE) input is low, the 8 outputs will be
in a normal state (high or low logic level) and
while high level the outputs will be in a high
impedance state.
The output control does not affect the internal
operation of flip flops; that is, the old data can be
retained or the new data can be entered even
while the outputs are off.
It has better speed performance at 3.3V than 5V
LSTTL family combined with the true CMOS low
power consumption.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
DESCRIPTION
The LVX374 is a low voltage CMOS OCTAL
D-TYPE FLIP FLOP with 3 STATE OUTPUT
NON INVERTING fabricated with sub-micron
silicon gate and double-layer metal wiring C
2
MOS
technology. It is ideal for low power and low noise
applications.
This 8 bit D-Type flip-flop is controlled by a clock
input (CK) and an output enable input (OE).
On the positive transition of the clock, the Q
PIN CONNECTION AND IEC LOGIC SYMBOLS
April 1999
1/10

74LVX374T相關(guān)型號(hào)PDF文件下載

  • 型號(hào)
    版本
    描述
    廠商
    下載
  • 英文版
    Quad 2-input NAND gate
    PHILIPS
  • 英文版
    Quad 2-input NAND gate
    PHILIPS [P...
  • 英文版
    Quad 2-input NOR gate
    Philips
  • 英文版
    Quad 2-input NAND gate
    Philips
  • 英文版
    Hex inverter
    Philips
  • 英文版
    Quad 2-input AND gate
    Philips
  • 英文版
    Triple 3-input NAND gate
    Philips
  • 英文版
    Triple 3-input AND gate
    Philips
  • 英文版
    Hex inverting Schmitt-trigger
    Philips
  • 英文版
    Dual 4-input NAND gate
    Philips
  • 英文版
    Triple 3-input NOR gate
    Philips
  • 英文版
    Quad 2-input OR gate
    Philips
  • 英文版
    Dual D-type flip-flop with set and reset; positive-edge trig...
    PHILIPS
  • 英文版
    Dual D-type flip-flop with set and reset; positive-edge trig...
    PHILIPS [NXP Se...
  • 英文版
    Quad 2-input EXCLUSIVE-OR gate
    Philips
  • 英文版
    QUADRUPLE 2 INPUT POSITIVE NAND GATES
    TI [Texas ...
  • 英文版
    Quad 2-input NAND gate
    PHILIPS
  • 英文版
    Quad 2-input NAND gate
    PHILIPS [N...
  • 英文版
    Quad 2-input NAND gate
    PHILIPS
  • 英文版
    Quad 2-input NAND gate
    PHILIPS [N...

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買(mǎi)家服務(wù)：
賣(mài)家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時(shí)間周一至周五
9:00-17:30

關(guān)注官方微信號(hào)，
第一時(shí)間獲取資訊。

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫(kù)提出的寶貴意見(jiàn)，您的參與是維庫(kù)提升服務(wù)的動(dòng)力！意見(jiàn)一經(jīng)采納，將有感恩紅包奉上哦！