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74LVX245T Datasheet

  • 74LVX245T

  • Single 8-bit Bus Transceiver

  • 66.32KB

  • 8頁(yè)

  • ETC

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廬
74LVX245
LOW VOLTAGE CMOS OCTAL BUS
TRANSCEIVER (3-STATE)
s
s
s
s
s
s
s
s
s
HIGH SPEED: t
PD
= 4.7 ns (TYP.) at V
CC
= 3.3V
COMPATIBLE WITH TTL LEVELS IN INPUTS
AND OUTPUTS
LOW POWER DISSIPATION:
I
CC
= 4
碌A(chǔ)
(MAX.) at T
A
= 25
o
C
LOW NOISE: V
OLP
= 0.3V (TYP.) at V
CC
= 3.3V
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 4 mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
鈮?/div>
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V (1.2VData Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 245
IMPROVED LATCH-UP IMMUNITY
M
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74LVX245M
74LVX245T
of data trasmission is determined by DIR input.
The enable input G can be used to disable the
device so that the buses are effectively isolated.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
IT IS PROHIBITED TO APPLY A SIGNAL TO A
TERMINAL WHEN IT IS IN OUTPUT MODE
AND WHEN A BUS TERMINAL IS FLOATING
(HIGH IMPEDANCE STATE) IT IS REQUESTED
TO FIX THE INPUT LEVEL BY MEANS OF
EXTERNAL PULL DOWN OR PULL UP
RESISTOR.
DESCRIPTION
The LVX245 is a low voltage CMOS OCTAL BUS
TRANSCEIVER (3-STATE) fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology. It is ideal for low
power and low noise 3.3V applications.
It has better speed performance at 3.3V than 5V
LSTTL family combined with the true CMOS low
power consumption.
This IC is intended for two-way asynchronous
communication between data buses; the direction
PIN CONNECTION AND IEC LOGIC SYMBOLS
March 1999
1/8

74LVX245T相關(guān)型號(hào)PDF文件下載

  • 型號(hào)
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  • 英文版
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    Quad 2-input NAND gate
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    Quad 2-input NOR gate
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    Hex inverter
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    Quad 2-input AND gate
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    Triple 3-input NAND gate
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    Triple 3-input AND gate
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    Hex inverting Schmitt-trigger
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    Dual 4-input NAND gate
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    Triple 3-input NOR gate
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    Quad 2-input OR gate
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    Dual D-type flip-flop with set and reset; positive-edge trig...
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    Dual D-type flip-flop with set and reset; positive-edge trig...
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    Quad 2-input EXCLUSIVE-OR gate
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    QUADRUPLE 2 INPUT POSITIVE NAND GATES
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    Quad 2-input NAND gate
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    Quad 2-input NAND gate
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    Quad 2-input NAND gate
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    Quad 2-input NAND gate
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