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74LVX174T Datasheet

  • 74LVX174T

  • Hex D-Type Flip-Flop

  • 74.23KB

  • 10頁(yè)

  • ETC

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74LVX174
HEX D-TYPE FLIP FLOP WITH CLEAR
WITH 5V TOLERANT INPUTS
s
s
s
s
s
s
s
s
s
s
HIGH SPEED:
f
MAX
= 180 MHz (TYP.) at V
CC
= 3.3V
5V TOLERANT INPUTS
POWER-DOWN PROTECTION ON INPUTS
INPUT VOLTAGE LEVEL:
V
IL
= 0.8V, V
IH
= 2V at V
CC
= 3V
LOW POWER DISSIPATION:
I
CC
= 4
碌A(chǔ)
(MAX.) at T
A
= 25
o
C
LOW NOISE:
V
OLP
= 0.3 V (TYP.) at V
CC
= 3.3V
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 4 mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
鈮?/div>
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 174
IMPROVED LATCH-UP IMMUNITY
M
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74LVX174M
74LVX174T
Information signals applied to D inputs are
transfered to the Q outputs on the positive going
edge of the clock pulse.
When the CLEAR input is held low, the Q outputs
are held low independently of the other inputs .
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
It has better speed performance at 3.3V than 5V
LS-TTL family combined with the true CMOS low
power consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
DESCRIPTION
The LVX174 is a low voltage CMOS HEX
D-TYPE FLIP FLOP WITH CLEAR NON
INVERTING fabricated with sub-micron silicon
gate and double-layer metal wiring C
2
MOS
technology. It is ideal for low power and low noise
3.3V applications.
PIN CONNECTION AND IEC LOGIC SYMBOLS
April 1999
1/10

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