鈥?/div>
High Speed: tPD = 6.8ns (Typ) at VCC = 3.3V
Low Power Dissipation: ICC = 2碌A(chǔ) (Max) at TA = 25擄C
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Low Noise: VOLP = 0.5V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300mA
ESD Performance: HBM > 2000V; Machine Model > 200V
VCC
14
A5
13
O5
12
A4
11
O4
10
A3
9
O3
8
1
A0
2
O0
3
A1
4
O1
5
A2
6
O2
7
GND
Figure 1. 14鈥揕ead Pinout
(Top View)
M SUFFIX
14鈥揕EAD SOIC EIAJ PACKAGE
CASE 965鈥?1
A0
A1
A2
A3
A4
A5
1
3
5
9
11
13
PIN NAMES
2
4
6
8
10
12
O0
O1
O2
Pins
An
On
Function
Data Inputs
Outputs
FUNCTION TABLE
O3
O4
O5
An
L
H
On
H
L
Figure 2. Logic Diagram
6/97
漏
Motorola, Inc. 1997
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