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74LVX132TTR Datasheet

  • 74LVX132TTR

  • Quad 2-input NAND Gate

  • 8頁

  • ETC

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74LVX132
LOW VOLTAGE CMOS QUAD 2-INPUT SCHMITT NAND GATE
WITH 5V TOLERANT INPUTS
s
s
s
s
s
s
s
s
s
s
s
HIGH SPEED :
t
PD
= 5.9ns (TYP.) at V
CC
= 3.3V
5V TOLERANT INPUTS
LOW POWER DISSIPATION:
I
CC
= 2
碌A
(MAX.) at T
A
=25擄C
TYPICAL HYSTERESIS : 0.7V at V
CC
= 3.3V
LOW NOISE:
V
OLP
= 0.3V (TYP.) at V
CC
= 3.3V
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 4mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
鈮?/div>
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V (1.2V Data Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 132
IMPROVED LATCH-UP IMMUNITY
POWER DOWN PROTECTION ON INPUTS
SOP
TSSOP
ORDER CODES
PACKAGE
SOP
TSSOP
TUBE
74LVX132M
T&R
74LVX132MTR
74LVX132TTR
DESCRIPTION
The 74LVX132 is a low voltage CMOS QUAD
2-INPUT SCHMITT NAND GATE fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology. It is ideal for low
power, battery operated and low noise 3.3V
applications. Power down protection is provided
on all inputs and 0 to 7V can be accepted on
inputs with no regard to the supply voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
This device can be used to interface 5V to 3V
system. It combines high speed performance with
the true CMOS low power consumption.
Pin configuration and function are the same as
those of the 74LVX00 but the 74LVX132 has
hysteresis.
This together with its schmitt trigger function
allows it to be used on line receivers with slow
rise/fall input signals.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
July 2001
1/8

74LVX132TTR 產品屬性

  • 74LVX132 View All Specifications

  • 1

  • 集成電路 (IC)

  • 邏輯 - 柵極和逆變器

  • 74LVX

  • 與非門

  • 4

  • 2

  • 施密特觸發(fā)器

  • 2 V ~ 3.6 V

  • 2µA

  • 4mA，4mA

  • 0.9V

  • 2.2V

  • 9ns @ 3V ~ 3.6V，50pF

  • -55°C ~ 125°C

  • 表面貼裝

  • 14-TSSOP

  • 14-TSSOP（0.173"，4.40mm 寬）

  • Digi-Reel®

  • 497-7113-6

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