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74LVX125T Datasheet

  • 74LVX125T

  • 4-Bit Buffer/Driver

  • 9頁

  • ETC

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廬
74LVX125
LOW VOLTAGE QUAD BUS BUFFERS (3-STATE)
WITH 5V TOLERANT INPUTS
s
s
s
s
s
s
s
s
s
s
HIGH SPEED: t
PD
= 4.4 ns (TYP.) at V
CC
= 3.3V
5V TOLERANT INPUTS
POWER-DOWN PROTECTION ON INPUTS
INPUT VOLTAGE LEVEL:
V
IL
= 0.8V, V
IH
= 2V at V
CC
= 3V
LOW POWER DISSIPATION:
I
CC
= 2
碌
A (MAX.) at T
A
= 25
o
C
LOW NOISE:
V
OLP
= 0.3 V (TYP.) at V
CC
= 3.3V
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 4 mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
鈮?/div>
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V (1.2V Data Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 125
IMPROVED LATCH-UP IMMUNITY
M
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74LVX125M
74LVX125T
This device requires the 3-STATE control input G
to be set high to place the output into the high
impedance state.
It has better speed performance at 3.3V than 5V
LS-TTL family combined with the true CMOS low
power consumption.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
DESCRIPTION
The LVX125 is a low voltage CMOS QUAD BUS
BUFFERS fabricated with sub-micron silicon gate
and
double-layer metal
wiring
C
2
MOS
technology. It is ideal for low power and low noise
3.3V applications.
PIN CONNECTION AND IEC LOGIC SYMBOLS
April 1999
1/9

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