74LVTH543 Low Voltage Octal Registered Transceiver with 3-STATE Outputs
April 2000
Revised April 2000
74LVTH543
Low Voltage Octal Registered Transceiver
with 3-STATE Outputs
General Description
The LVTH543 octal transceiver contains two sets of D-type
latches for temporary storage of data flowing in either
direction. Separate Latch Enable and Output Enable inputs
are provided for each register to permit independent con-
trol of inputting and outputting in either direction of data
flow.
The LVTH543 data inputs include bushold, eliminating the
need for external pull-up resistors to hold unused inputs.
This octal registered transceiver is designed for low-volt-
age (3.3V) V
CC
applications, but with the capability to pro-
vide a TTL interface to a 5V environment. The LVTH543 is
fabricated with an advanced BiCMOS technology to
achieve high speed operation similar to 5V ABT while
maintaining a low power dissipation.
Features
s
Input and output interface capability to systems at
5V V
CC
s
Bushold data inputs eliminate the need for external pull-
up resistors to hold unused inputs
s
Live insertion/extraction permitted
s
Power Up/Down high impedance provides glitch-free
bus loading
s
Outputs source/sink
鈭?2
mA/+64 mA
s
Functionally compatible with the 74 series 543
s
Latch-up performance exceeds 500 mA
Ordering Code:
Order Number
74LVTH543WM
74LVTH543MTC
Package Number
M24B
MTC24
Package Description
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300鈥?Wide
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter 鈥淴鈥?to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
OEAB, OEBA
LEAB, LEBA
CEAB, CEBA
A
0
鈥揂
7
Description
Output Enable Inputs
Latch Enable Inputs
Chip Enable Inputs
Side A Inputs or
3-STATE Outputs
B
0
鈥揃
7
Side B Inputs or
3-STATE Outputs
漏 2000 Fairchild Semiconductor Corporation
DS012448
www.fairchildsemi.com