音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

74LVTH16952MEAX Datasheet

  • 74LVTH16952MEAX

  • Low Voltage 16-Bit Registered Transceiver with 3-STATE Outpu...

  • 8頁

  • FAIRCHILD

掃碼查看芯片數(shù)據(jù)手冊

上傳產(chǎn)品規(guī)格書

PDF預(yù)覽

74LVT16952 鈥?74LVTH16952 Low Voltage 16-Bit Registered Transceiver with 3-STATE Outputs
January 2000
Revised October 2001
74LVT16952 鈥?74LVTH16952
Low Voltage 16-Bit Registered Transceiver
with 3-STATE Outputs
General Description
The LVT16952 and LVTH16952 are 16-bit registered
transceivers. Two 8-bit back to back registers store data
flowing in both directions between two bidirectional buses.
Separate clock, clock enable, and output enable signals
are provided for each register.
The LVTH16952 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
The registered transceiver is designed for low-voltage
(3.3V) V
CC
applications, but with the capability to provide a
TTL interface to a 5V environment.
The LVT16952 and LVTH16952 are fabricated with an
advanced BiCMOS technology to achieve high speed oper-
ation similar to 5V ABT while maintaining low power dissi-
pation.
Features
s
Input and output interface capability to systems at
5V V
CC
s
Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH16952)
s
Live insertion/extraction permitted
s
Power Up/Down high impedance provides glitch-free
bus loading
s
Outputs source/sink
鈭?/div>
32 mA/
+
64 mA
s
Functionally compatible with the 74 series 16952
s
Latch-up conforms to JEDEC JED78
s
ESD performance:
Human-body model
>
2000V
Machine model
>
200V
Charged-device model
>
1000V
Ordering Code:
Order Number
74LVT16952MEA
(Preliminary)
74LVT16952MTD
(Preliminary)
74LVTH16952MEA
74LVTH16952MTD
Package Number
MS56A
MTD56
MS56A
MTD56
Package Description
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
漏 2001 Fairchild Semiconductor Corporation
DS500103
www.fairchildsemi.com

74LVTH16952MEAX 產(chǎn)品屬性

  • 1,000

  • 集成電路 (IC)

  • 邏輯 - 緩沖器,驅(qū)動(dòng)器,接收器,收發(fā)器

  • 74LVTH

  • 收發(fā)器,非反相

  • 2

  • 8

  • 32mA,64mA

  • 2.7 V ~ 3.6 V

  • -40°C ~ 85°C

  • 表面貼裝

  • 56-BSSOP(0.295",7.50mm 寬)

  • 56-SSOP

  • 帶卷 (TR)

74LVTH16952MEAX相關(guān)型號(hào)PDF文件下載

  • 型號(hào)
    版本
    描述
    廠商
    下載
  • 英文版
    Quad 2-input NAND gate
    PHILIPS
  • 英文版
    Quad 2-input NAND gate
    PHILIPS [P...
  • 英文版
    Quad 2-input NOR gate
    Philips
  • 英文版
    Quad 2-input NAND gate
    Philips
  • 英文版
    Hex inverter
    Philips
  • 英文版
    Quad 2-input AND gate
    Philips
  • 英文版
    Triple 3-input NAND gate
    Philips
  • 英文版
    Triple 3-input AND gate
    Philips
  • 英文版
    Hex inverting Schmitt-trigger
    Philips
  • 英文版
    Dual 4-input NAND gate
    Philips
  • 英文版
    Triple 3-input NOR gate
    Philips
  • 英文版
    Quad 2-input OR gate
    Philips
  • 英文版
    Dual D-type flip-flop with set and reset; positive-edge trig...
    PHILIPS
  • 英文版
    Dual D-type flip-flop with set and reset; positive-edge trig...
    PHILIPS [NXP Se...
  • 英文版
    Quad 2-input EXCLUSIVE-OR gate
    Philips
  • 英文版
    QUADRUPLE 2 INPUT POSITIVE NAND GATES
    TI [Texas ...
  • 英文版
    Quad 2-input NAND gate
    PHILIPS
  • 英文版
    Quad 2-input NAND gate
    PHILIPS [N...
  • 英文版
    Quad 2-input NAND gate
    PHILIPS
  • 英文版
    Quad 2-input NAND gate
    PHILIPS [N...

掃碼下載APP,
一鍵連接廣大的電子世界。

在線人工客服

買家服務(wù):
賣家服務(wù):
技術(shù)客服:

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時(shí)間周一至周五
9:00-17:30

關(guān)注官方微信號(hào),
第一時(shí)間獲取資訊。

建議反饋

聯(lián)系人:

聯(lián)系方式:

按住滑塊,拖拽到最右邊
>>
感謝您向阿庫提出的寶貴意見,您的參與是維庫提升服務(wù)的動(dòng)力!意見一經(jīng)采納,將有感恩紅包奉上哦!