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74LVTH16240DGGRE4 Datasheet

  • 74LVTH16240DGGRE4

  • 3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

  • 184.55KB

  • 11頁

  • TI

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SN54LVTH16240, SN74LVTH16240
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS684C 鈥?MARCH 1997 鈥?REVISED APRIL 1999
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Members of the Texas Instruments
Widebus
鈩?/div>
Family
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation
Support Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
3.3-V V
CC
)
Support Unregulated Battery Operation
Down to 2.7 V
Typical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
= 3.3 V, T
A
= 25擄C
I
off
and Power-Up 3-State Support Hot
Insertion
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Distributed V
CC
and GND Pin Configuration
Minimizes High-Speed Switching Noise
Flow-Through Architecture Optimizes PCB
Layout
Latch-Up Performance Exceeds 500 mA Per
JESD 17
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Package Options Include Plastic Shrink
Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
SN54LVTH16240 . . . WD PACKAGE
SN74LVTH16240 . . . DGG OR DL PACKAGE
(TOP VIEW)
1OE
1Y1
1Y2
GND
1Y3
1Y4
V
CC
2Y1
2Y2
GND
2Y3
2Y4
3Y1
3Y2
GND
3Y3
3Y4
V
CC
4Y1
4Y2
GND
4Y3
4Y4
4OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
2OE
1A1
1A2
GND
1A3
1A4
V
CC
2A1
2A2
GND
2A3
2A4
3A1
3A2
GND
3A3
3A4
V
CC
4A1
4A2
GND
4A3
4A4
3OE
description
These 16-bit buffers/drivers are designed specifically for low-voltage (3.3-V) V
CC
operation, but with the
capability to provide a TTL interface to a 5-V system environment.
The 鈥橪VTH16240 devices are designed specifically to improve both the performance and density of 3-state
memory address drivers, clock drivers, and bus-oriented receivers and transmitters.
The devices can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. The devices provide
inverting outputs and symmetrical active-low output-enable (OE) inputs.
When V
CC
is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V
CC
through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
Copyright
漏
1999, Texas Instruments Incorporated
鈥?/div>
DALLAS, TEXAS 75265
1

74LVTH16240DGGRE4 產(chǎn)品屬性

  • 2,000

  • 集成電路 (IC)

  • 邏輯 - 緩沖器，驅(qū)動器，接收器，收發(fā)器

  • 74LVTH

  • 緩沖器/線路驅(qū)動器，非反相

  • 4

  • 4

  • 32mA，64mA

  • 2.7 V ~ 3.6 V

  • -40°C ~ 85°C

  • 表面貼裝

  • 48-TFSOP（0.240"，6.10mm 寬）

  • 48-TSSOP

  • 帶卷 (TR)

74LVTH16240DGGRE4相關(guān)型號PDF文件下載

  • 型號
    版本
    描述
    廠商
    下載
  • 英文版
    Quad 2-input NAND gate
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    Quad 2-input NAND gate
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    Quad 2-input NOR gate
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    Quad 2-input NAND gate
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    Hex inverter
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    Quad 2-input AND gate
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  • 英文版
    Triple 3-input NAND gate
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    Triple 3-input AND gate
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  • 英文版
    Hex inverting Schmitt-trigger
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    Dual 4-input NAND gate
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  • 英文版
    Triple 3-input NOR gate
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  • 英文版
    Quad 2-input OR gate
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  • 英文版
    Dual D-type flip-flop with set and reset; positive-edge trig...
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  • 英文版
    Dual D-type flip-flop with set and reset; positive-edge trig...
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    Quad 2-input EXCLUSIVE-OR gate
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  • 英文版
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    TI [Texas ...
  • 英文版
    Quad 2-input NAND gate
    PHILIPS
  • 英文版
    Quad 2-input NAND gate
    PHILIPS [N...
  • 英文版
    Quad 2-input NAND gate
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    Quad 2-input NAND gate
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