74LVT162240 鈥?74LVTH162240 Low Voltage 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs and 25鈩?/div>
Series Resistors in the Outputs
June 1999
Revised June 1999
74LVT162240 鈥?74LVTH162240
Low Voltage 16-Bit Inverting Buffer/Line Driver
with 3-STATE Outputs and
25鈩?Series Resistors in the Outputs
General Description
The LVT162240 and LVTH162240 contain sixteen inverting
buffers with 3-STATE outputs designed to be employed as
a memory and address driver, clock driver, or bus oriented
transmitter/receiver. The device is nibble controlled. Indi-
vidual 3-STATE control inputs can be shorted together for
8-bit or 16-bit operation.
The LVT162240 and LVTH162240 are designed with
equivalent 25鈩?series resistance in both the HIGH and
LOW states of the output. This design reduces line noise in
applications such as memory address drivers, clock driv-
ers, and bus transceivers/transmitters.
The LVTH162240 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These inverting buffers and line drivers are designed for
low-voltage (3.3V) V
CC
applications, but with the capability
to provide a TTL interface to a 5V environment. The
LVT162240 and LVTH162240 are fabricated with an
advanced BiCMOS technology to achieve high speed oper-
ation similar to 5V ABT while maintaining a low power dis-
sipation.
Features
s
Input and output interface capability to systems at
5V V
CC
s
Outputs include equivalent series resistance of 25鈩?to
make external termination resistors unnecessary and
reduce overshoot and undershoot
s
Bushold data inputs eliminate the need for external pull-
up resistors to hold unused inputs (74LVTH162240),
also available without bushold feature (74LVT162240).
s
Live insertion/extraction permitted
s
Power Up/Down high impedance provides glitch-free
bus loading
s
Functionally compatible with the 74 series 162240
s
Latch-up performance exceeds 500 mA
Ordering Code:
Order Number
74LVT162240MEA
74LVT162240MTD
74LVTH162240MEA
74LVTH162240MTD
Package Number
MS48A
MTD48
MS48A
MTD48
Package Description
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300鈥?Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300鈥?Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter 鈥淴鈥?to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
OE
n
I
0
鈥揑
15
O
0
鈥揙
15
Description
Output Enable Inputs (Active LOW)
Inputs
3-STATE Outputs
漏 1999 Fairchild Semiconductor Corporation
DS012490
www.fairchildsemi.com
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