鈥?/div>
Latch鈥搖p protection exceeds 500mA per
JEDEC JC40.2 Std 17
independently by Enable (E) and Output
Enable (OE) control gates.
The data on the D inputs are transferred to
the latch outputs when the Latch Enable (E)
input is High. The latch remains transparent
to the data inputs while E is High, and stores
the data that is present one setup time before
the High-to-Low enable transition.
The 3-State output buffers are designed to
drive heavily loaded 3-State buses, MOS
memories, or MOS microprocessors. The
active-Low Output Enable (OE) controls all
eight 3-State buffers independent of the latch
operation.
When OE is Low, the latched or transparent
data appears at the outputs. When OE is
High, the outputs are in the High-impedance
鈥漁FF鈥?state, which means they will neither
drive nor load the bus.
鈥?/div>
Supports mixed鈥搈ode signal operation; 5V
鈥?/div>
Bus鈥揾old inputs eliminate the need for
input and output voltages with 3.3V V
CC
external pull-up resistors to hold unused
pins
鈥?/div>
ESD protection exceeds 2000 V per MIL
STD 883 Method 3015 and 200 V per
Machine Model
DESCRIPTION
The 74LVT373 device is designed specifically
for low鈥搗oltage (3.3V) V
CC
operation, but can
provide a TTL interface to a 5V system
environment.
The 74LVT373 high-performance BiCMOS
device combines zero static and low dynamic
power dissipation with high speed and high
output drive.
The 74LVT373 device is an octal transparent
latch coupled to eight 3-State output buffers.
The two sections of the device are controlled
鈥?/div>
Live insertion/extraction permitted
鈥?/div>
No bus current loading when output is tied
to 5V bus
鈥?/div>
8鈥揵it transparent latch
鈥?/div>
3-State output buffers
鈥?/div>
Zero-static power dissipation
鈥?/div>
Pin and function compatibility with ABT
鈥?/div>
AC and DC performance compatibility with
ABT
QUICK REFERENCE DATA
SYMBOL
t
PLH
t
PHL
C
IN
C
OUT
I
CCZ
PARAMETER
Propagation delay
Dn to Qn
Input capacitance
Output capacitance
Total supply current
CONDITIONS
T
amb
= 25擄C; GND = 0V
C
L
= 50pF; V
CC
= 5V
V
I
= 0V or V
CC
V
I
= 0V or V
CC
Outputs disabled; V
CC
=5.5V
TYPICAL
4.2
4
7
50
UNIT
ns
pF
pF
碌A
ORDERING INFORMATION
PACKAGES
20鈥揚in Plastic SOL
20鈥揚in Plastic SSOP
20鈥揚in Plastic TSSOP
TEMPERATURE RANGE
-40擄C to +85擄C
-40擄C to +85擄C
-40擄C to +85擄C
ORDER CODE
74LVT373D
74LVT373DB
74LVT373PW
DRAWING NUMBER
0172D
1640B
TBD
PIN DESCRIPTION
PIN NUMBER
1
3, 4, 7, 8, 13, 14, 17, 18
2, 5, 6, 9, 12, 15, 16, 19
11
10
20
SYMBOL
OE
D0-D7
Q0-Q7
E
GND
V
CC
Output enable input (active-Low)
Data inputs
Data outputs
Enable input (active-High)
Ground (0V)
Positive supply voltage
FUNCTION
July 1993
2
74LVT373DB相關(guān)型號PDF文件下載
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型號
版本
描述
廠商
下載
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