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74LVT125DB Datasheet

  • 74LVT125DB

  • 3.3 V quad buffer; 3-state

  • 15頁

  • PHILIPS

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74LVT125
3.3 V quad buffer; 3-state
Rev. 05 鈥?10 February 2005
Product data sheet
1. General description
The LVT125 is a high-performance BiCMOS product designed for V
CC
operation at 3.3 V.
This device combines low static and dynamic power dissipation with high speed and high
output drive. The 74LVT125 device is a quad buffer that is ideal for driving bus lines. The
device features four output enable inputs (1OE, 2OE, 3OE and 4OE), each controlling one
of the 3-state outputs.
2. Features
s
s
s
s
s
s
s
s
s
s
s
Quad bus interface
3-state buffers
Output capability: +64 mA and
鈭?2
mA
TTL input and output switching levels
Input and output interface capability to systems at 5 V supply
Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused
inputs
Live insertion and extraction permitted
No bus current loading when output is tied to 5 V bus
Power-up 3-state
Latch-up protection:
x
JESD78: exceeds 500 mA
ESD protection:
x
MIL STD 883 method 3015: exceeds 2000 V
x
Machine model: exceeds 200 V
3. Quick reference data
Table 1:
Quick reference data
GND = 0 V; T
amb
= 25
擄
C.
Symbol Parameter
t
PLH
t
PHL
C
I
C
O
I
CC
Conditions
Min
-
-
-
-
-
Typ
2.7
2.9
4
8
0.13
Max
-
-
-
-
-
Unit
ns
ns
pF
pF
mA
propagation delay nA to nY C
L
= 50 pF; V
CC
= 3.3 V
propagation delay nA to nY C
L
= 50 pF; V
CC
= 3.3 V
input capacitance
output capacitance
quiescent supply current
V
I
= 0 V or 3.0 V
outputs disabled;
V
O
= 0 V or 3.0 V
outputs disabled;
V
CC
= 3.6 V

74LVT125DB 產(chǎn)品屬性

  • NXP

  • 緩沖器和線路驅(qū)動器

  • 4

  • 4

  • Non-Inverting

  • 3.6 V

  • 2.7 V

  • + 85 C

  • SMD/SMT

  • SOT-337-14

  • Tube

  • - 32 mA

  • LVT

  • BiCMOS

  • 64 mA

  • - 40 C

  • 4

  • 3-State

  • 2.9 ns at 3.3 V

  • 78

  • 74LVT125DB,112

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