74LVQ373 Low Voltage Octal Transparent Latch with 3-STATE Outputs
February 1992
Revised June 2001
74LVQ373
Low Voltage Octal Transparent Latch
with 3-STATE Outputs
General Description
The LVQ373 consists of eight latches with 3-STATE out-
puts for bus organized system applications. The latches
appear transparent to the data when Latch Enable (LE) is
HIGH. When LE is low, the data satisfying the input timing
requirements is latched. Data appears on the bus when the
Output Enable (OE) is LOW. When OE is HIGH, the bus
output is in the high impedance state.
Features
s
Ideal for low power/low noise 3.3V applications
s
Implements patented EMI reduction circuitry
s
Available in SOIC JEDEC, SOIC EIAJ and QSOP
packages
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
s
Improved latch-up immunity
s
Guaranteed incident wave switching into 75
鈩?/div>
s
4 kV minimum ESD immunity
Ordering Code:
Order Number
74LVQ373SC
74LVQ373SJ
74LVQ373QSC
Package Number
M20B
M20D
MQA20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide
Devices also available in Tape and Reel. Specify by appending suffix letter 鈥淴鈥?to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Truth Table
Inputs
Outputs
D
n
X
L
H
X
O
n
Z
L
H
O
0
Pin Descriptions
Pin Names
D
0
鈥揇
7
LE
OE
O
0
鈥揙
7
Description
Data Inputs
Latch Enable Input
Output Enable Input
3-STATE Latch Outputs
LE
X
H
H
L
OE
H
L
L
L
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
Z
=
High Impedance
X
=
Immaterial
O
0
=
Previous O
0
before HIGH to Low transition of Latch Enable
漏 2001 Fairchild Semiconductor Corporation
DS011359
www.fairchildsemi.com
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