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74LVQ280 Datasheet

  • 74LVQ280

  • 9 BIT PARITY GENERATOR

  • 232.04KB

  • 8頁

  • STMICROELECTRONICS   STMICROELECTRONICS

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74LVQ280
9 BIT PARITY GENERATOR
s
s
s
s
s
s
s
s
s
s
s
HIGH SPEED:
t
PD
= 8 ns (TYP.) at V
CC
= 3.3 V
COMPATIBLE WITH TTL OUTPUTS
LOW POWER DISSIPATION:
I
CC
= 2碌A(chǔ)(MAX.) at T
A
=25擄C
LOW NOISE:
V
OLP
= 0.3V (TYP.) at V
CC
= 3.3V
75鈩?TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 12mA (MIN) at V
CC
= 3.0 V
PCI BUS LEVELS GUARANTEED AT 24 mA
BALANCED PROPAGATION DELAYS:
t
PLH
鈮?/div>
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 280
IMPROVED LATCH-UP IMMUNITY
SOP
TSSOP
ORDER CODES
PACKAGE
SOP
TSSOP
TUBE
74LVQ280M
T&R
74LVQ280MTR
74LVQ280TTR
DESCRIPTION
The 74LVQ280 is a low voltage CMOS 9 BIT
PARITY GENERATOR fabricated with sub-micron
silicon gate and double-layer metal wiring C
2
MOS
technology. It is ideal for low power and low noise
3.3V applications.
It is composed of nine data inputs (A to I) and odd/
even parity outputs (危ODD and
危EVEN).
The nine
PIN CONNECTION AND IEC LOGIC SYMBOLS
data inputs control the output conditions. When
the number of high level input is odd,
危ODD
output is kept high and
危EVEN
output low.
Conversely, when the number of high level is
even,
危EVEN
output is kept high and
危ODD
low.
The IC generates either odd or even parity making
it flexible application. The word-length capability is
easily expanded by cascading.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
July 2001
1/8

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