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74LVQ273 Datasheet

  • 74LVQ273

  • OCTAL D-TYPE FLIP FLOP WITH CLEAR

  • 75.18KB

  • 10頁

  • STMICROELECTRONICS   STMICROELECTRONICS

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廬
74LVQ273
OCTAL D-TYPE FLIP FLOP WITH CLEAR
s
s
s
s
s
s
s
s
s
s
s
HIGH SPEED:
f
MAX
= 150 MHz (TYP.) at V
CC
= 3.3V
COMPATIBLE WITH TTL OUTPUT
LOW POWER DISSIPATION:
I
CC
= 4
碌A(chǔ)
(MAX.) at T
A
= 25
o
C
LOW NOISE:
V
OLP
= 0.4 V (TYP.) at V
CC
= 3.3V
75鈩?TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 12 mA (MIN)
PCI BUS LEVELS GUARANTEED AT 24mA
BALANCED PROPAGATION DELAYS:
t
PLH
鈮?/div>
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V (1.2V Data Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 273
IMPROVED LATCH-UP IMMUNITY
M
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74LVQ273M
74LVQ273T
Information signals applied to D inputs are
transfered to the Q outputs on the positive going
edge of the clock pulse.
When the CLEAR inputs is held low, the Q
outputs are held low independentely of the other
inputs .
It has better speed performance at 3.3V than 5V
LS-TTL family combined with the true CMOS low
power consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
DESCRIPTION
The LVQ273 is a low voltage CMOS OCTAL
D-TYPE FLIP FLOP WITH CLEAR fabricated
with sub-micron silicon gate and double-layer
metal wiring C
2
MOS technology. It is ideal for low
power and low noise 3.3V applications.
PIN CONNECTION AND IEC LOGIC SYMBOLS
February 1999
1/10

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