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74LVQ174M Datasheet

  • 74LVQ174M

  • HEX D-TYPE FLIP FLOP WITH CLEAR

  • 10頁

  • STMICROELECTRONICS   STMICROELECTRONICS

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廬
74LVQ174
HEX D-TYPE FLIP FLOP WITH CLEAR
s
s
s
s
s
s
s
s
s
s
s
HIGH SPEED:
f
MAX
= 150 MHz (TYP.) at V
CC
= 3.3V
COMPATIBLE WITH TTL OUTPUTS
LOW POWER DISSIPATION:
I
CC
= 4
碌A(chǔ)
(MAX.) at T
A
= 25
o
C
LOW NOISE:
V
OLP
= 0.3 V (TYP.) at V
CC
= 3.3V
75鈩?TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 12 mA (MIN)
PCI BUS LEVELS GUARANTEED AT 24mA
BALANCED PROPAGATION DELAYS:
t
PLH
鈮?/div>
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V (1.2V Data Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 174
IMPROVED LATCH-UP IMMUNITY
M
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74LVQ174M
74LVQ174T
3.3V applications.
Information signals applied to D inputs are
transfered to the Q outputs on the positive going
edge of the clock pulse.
When the CLEAR input is held low, the Q outputs
are held low independentely of the other inputs .
It has better speed performance at 3.3V than 5V
LS-TTL family combined with the true CMOS low
power consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
DESCRIPTION
The LVQ174 is a low voltage CMOS HEX
D-TYPE FLIP FLOP WITH CLEAR NON
INVERTING fabricated with sub-micron silicon
gate and double-layer metal wiring C
2
MOS
technology. It is ideal for low power and low noise
PIN CONNECTION AND IEC LOGIC SYMBOLS
February 1999
1/10

74LVQ174M 產(chǎn)品屬性

  • STMicroelectronics

  • 1

  • LVQ

  • CMOS

  • Non-Inverting

  • Single-Ended

  • 11 ns

  • - 24 mA

  • 3.6 V

  • + 125 C

  • SMD/SMT

  • Tube

  • - 55 C

  • 6

  • 6

  • 50

  • 2 V

74LVQ174M相關(guān)型號(hào)PDF文件下載

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